CAT24C256 Datasheet, PDF (2/14 Pages) Catalyst Semiconductor – 256-Kb I2C CMOS Serial EEPROM

CAT24C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V_CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V_CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
N_END (Note 3) Endurance
1,000,000
Program/Erase Cycles
T_DR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V_CC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
I_CCR
I_CC
I_SB
I_L
V_IL
V_IH
V_OL1
V_OL2
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Read, f_SCL = 400 kHz
Write, f_SCL = 400 kHz
All I/O Pins at GND or V_CC
Pin at GND or V_CC
V_CC ≥ 2.5 V, I_OL = 3.0 mA
V_CC < 2.5 V, I_OL = 1.0 mA
T_A = −40°C to +85°C
T_A = −40°C to +125°C
T_A = −40°C to +85°C
T_A = −40°C to +125°C
Min
−0.5
V_CC x 0.7
Max
1
3
1
2
1
2
V_CC x 0.3
V_CC + 0.5
0.4
0.2
Units
mA
mA
mA
mA
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4) SDA I/O Pin Capacitance
V_IN = 0 V
8
pF
C_IN (Note 4) Input Capacitance (other pins)
V_IN = 0 V
6
pF
I_WP (Note 5)
WP Input Current
(Product Revision C and higher)
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.3 V
130
mA
120
V_IN < V_IH, V_CC = 1.8 V
80
V_IN > V_IH
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source. The
variable WP input impedance is available only for Die Rev. C and higher.
http://onsemi.com
2