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CAT24C164WI-G Datasheet, PDF (2/14 Pages) ON Semiconductor – 16 kb CMOS Serial EEPROM, Cascadable | |||
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CAT24C164
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
â65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
â0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than â0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than â1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
NEND (Note 3) Endurance
1,000,000
Program/Erase Cycles
TDR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECâQ100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = â40°C to +85°C, unless otherwise speciï¬ed.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
1
mA
ICCW
ISB
IL
VIL
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Write, fSCL = 400 kHz
All I/O Pins at GND or VCC
Pin at GND or VCC
â0.5
1
mA
1
mA
1
mA
VCC x 0.3
V
VIH
VOL1
VOL2
Input High Voltage
Output Low Voltage
Output Low Voltage
VCC ⥠2.5 V, IOL = 3.0 mA
VCC < 2.5 V, IOL = 1.0 mA
VCC x 0.7
VCC + 0.5
V
0.4
V
0.2
V
Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.8 V to 5.5 V, TA = â40°C to +85°C, unless otherwise speciï¬ed.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 4) SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN (Note 4) Input Capacitance (other pins)
VIN = 0 V
6
pF
IWP (Note 5) WP Input Current
VIN < VIH, VCC = 5.5 V
200
mA
VIN < VIH, VCC = 3.3 V
150
VIN < VIH, VCC = 1.8 V
100
VIN > VIH
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECâQ100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pullâdown is relatively strong;
therefore the external driver must be able to supply the pullâdown current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pullâdown reverts to a weak current source.
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