AND8044 Datasheet, PDF (2/4 Pages) ON Semiconductor – Single-Channel 1206A ChipFET TM Power MOSFET Recommended Pad Pattern and Thermal Performance

AND8044/D
EVALUATION BOARD FOR THE SINGLE 1206A
The ChipFET 1206A evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around the six drain leads on the top–side –
approximately 0.0482 sq. in. 31.1 sq. mm – and vias added
through to the underside of the board, again with a
maximized copper pad area of approximately the
board–size dimensions. The outer package outline is for the
8–pin DIP, which will allow test sockets to be used to assist
in testing.
The thermal performance of the 1206A on this board has
been measured with the results following on the next page.
The testing included comparison with the minimum
recommended footprint on the evaluation board–size pcb
and the industry standard one–inch square FR4 pcb with
copper on both sides of the board.
Front of Board
CCHhIPipFFEETT™t
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D
Back of Board
D
D
D
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1206A
Figure 4. Evaluation Board
THERMAL PERFORMANCE
Junction–to–Foot Thermal Resistance
(the Package Performance)
Thermal performance for the 1206A ChipFET measured
as junction–to–foot thermal resistance is 15_C/W typical,
20_C/W maximum for the single device. The “foot” is the
drain lead of the device as it connects with the body. This
is identical to the SO–8 package R_θJF performance, a feat
made possible by shortening the leads to the point where
they become only a small part of the total footprint area.
Junction–to–Ambient Thermal Resistance
(dependent on pcb size)
The R_θJA typical for the single–channel 1206A ChipFET
is 80_C/W steady state, compared with 68_C/W for the
SO–8. Maximum ratings are 95_C/W for the 1206–8
versus 80_C/W for the SO–8.
Testing
To aid comparison further, Figure 5 illustrates ChipFET
1206A thermal performance on two different board sizes
and three different pad patterns. The results display the
thermal performance out to steady state and produce a
graphic account of how an increased copper pad area for the
drain connections can enhance thermal performance. The
measured steady state values of R_θJA for the single 1206A
ChipFET are:
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ Minimum recommended pad pattern (see Figure 3)
on the evaluation board size of 0.5 in. x 0.6 in.
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ _{The evaluation board with the pad pattern described}
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ _{on Figure 4}
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ _{Industry standard 1″ square pcb with maximum}
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ _{copper both sides.}
156_C/W
111_C/W
78_C/W
The results show that a major reduction can be made in
the thermal resistance by increasing the copper drain area.
In this example, a 45_C/W reduction was achieved without
having to increase the size of the board. If increasing board
size is an option, a further 33_C/W reduction was obtained
by maximizing the copper from the drain on the larger 1″
square pcb.
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