82P33731 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – Composite clock inputs

82P33731 Short Form Datasheet
DESCRIPTION
The 82P33731 Synchronous Equipment Timing Source (SETS) for 10G Synchronous Ethernet (SyncE) provides tools to manage timing refer-
ences, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33731 meets the requirements of ITU-T
G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jit-
ter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI,
SONET/SDH and PDH interfaces.
The 82P33731 accepts six differential reference inputs and six single ended reference inputs that can operate at common GNSS, Ethernet,
SONET/SDH and PDH frequencies that range from 1 Pulse Per Second (PPS) to 650 MHz. The device also provides two Alternate Mark Inversion
(AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continually moni-
tored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to both Digital PLLs (DPLLs). The
active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allow-
ances and based on the reference monitors and LOS inputs.
The 82P33731 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 can lock to the clock reference and
align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs
to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can
have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame sync and multi-frame sync outputs with a sync
input without the need use a low bandwidth setting to lock directly to the sync input.
The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on
the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre-
quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data
acquired while in Locked mode to generate accurate frequencies when input references are not available.
The 82P33731 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-
mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the
DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.
When used with a suitable system clock, DPLL1 meets the frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, tran-
sient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, Telcordia GR-
1244 Stratum 3 (S3), Telcordia GR-253-CORE S3 and SONET Minimum Clock (SMC).
DPLL1 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be used to lock the
DPLL directly to a 1 PPS reference. The 92 mHz bandwidth can be used for G.8262/G.813 Option 2, or Telcordia GR-253-CORE S3, or SMC applica-
tions. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used for G.8262/G.813 Option 1 applications. The bandwidth of 1.1 Hz or 2.2 Hz can be
used for Telcordia GR-1244-CORE S3 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.
DPLL2 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048
MHz synchronization interface clock.
For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to
output clocks for the T4 reference point.
Clocks generated by DPLL1 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output
clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.
Clocks generated by DPLL1 can be passed through APLL3 which is a voltage controlled crystal oscillator (VCXO) based jitter attenuating APLL.
APLL3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. The output clocks generated by
APLL3 are suitable for serial 40GBASE-R and lower rate interfaces.
The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con-
nected to either DPLL1 or DPLL3.
All 82P33731 control and status registers are accessed through an I2C slave microprocessor interface. For configuring the DPLLs, APLL1 and
APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset. APLL3 must be configured via the I2C
slave interface.
©2016 Integrated Device Technology, Inc.
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Revision 4, March 20, 2016