NCP1605BDR2G Datasheet, PDF (19/32 Pages) ON Semiconductor – Enhanced, High Voltage and Efficient Standby Mode, Power Factor Controller

NCP1605, NCP1605A, NCP1605B
V_in
I_in
L
Inductor Current
V_out
I_pk
t₁
t₂
t₃
T
Time
Figure 53. PFC Boost Converter
Figure 54. Inductor Current in DCM
The NCP1605 operates in voltage mode. As portrayed by
Figure 55, the MOSFET on time t₁ is controlled by the
signal V_ton generated by the regulation block and the Pin
4 ramp as follows:
t1
+
Cpin7 @ VTON
Ipin7
(eq. 2)
The charge current that is sourced by Pin 7
[I_pin7 = 60 mA/V² * (V_Pin4)²] is constant at a given input
voltage (V_Pin4 is proportional to the output voltage). C_pin7
that is the capacitor connected between Pin 7 and ground
is also a constant. Hence, the power factor correction is
achieved when the V_TON (t₁ + t₂)/T term is constant.
The output of the regulation block (V_CONTROL) is
linearly changed into a signal (V_REGUL) varying between
0 and 1 V. (V_REGUL) is the voltage that is injected into the
PWM section to modulate the MOSFET duty−cycle.
However, like the NCP1601, the NCP1605 inserts some
circuitry that processes (V_REGUL) to form the signal
(V_TON) that is used in the PWM section instead of
(V_REGUL) (see Figure 56). (V_TON) is modulated in response
to the dead−time sensed during the precedent current
cycles, that is, for a proper shaping of the ac line current
(refer to NCP1601 data sheet). This modulation leads to:
VTON
+
T
@ VREGUL
t1 ) t2
or :
VTON
@
t1
)
T
t2
+
VREGUL
(eq. 3)
Given the regulation low bandwidth of the PFC systems,
(V_CONTROL) and then (V_REGUL) are slow varying signals.
Hence, the (V_TON * (t₁ + t₂)/T) term is substantially
constant. Provided that in addition, (t1) is proportional to
(V_TON), equation (1) leads to: (I_in = k * V_in), where k is a
constant. More exactly:
ƪ ƫ ^{Iin + k @ Vin}
where : k + constant +
Cpin7 @ VREGUL
120 m @ L @ (Vpin2)²
(eq. 4)
The input current is then proportional to the input
voltage. Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CRM
case. This condition is just a particular case of this
functioning where (t₃ = 0), which leads to (t₁ + t₂ = T) and
(V_TON = V_REGUL). That is why the NCP1605 automatically
adapts to the conditions and jumps from DCM and CRM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
Remark: Like in the NCP1601, the “V_TON processing
circuit” is “informed” when there is an OVP condition, not
to over−dimension V_TON in that conditions. Otherwise, an
OVP sequence would be viewed as a dead−time phase by
the circuit and V_TON would inappropriately increase to
compensate it.
Similarly, the “V_TON processing circuit” is inhibited for
a skip sequence not to over−dimension “V_TON” in this case
(refer to Figure 56).
Closed When
Output Low
I_ch
PWM Comparator
Turns Off MOSFET
V_ton
C_ramp
V_ton
Ramp Voltage
PWM Outtage
Figure 55. PWM Circuit and Timing Diagram
timing capacitor
saw−tooth
PWM
comparator
+
to PWM latch
−
OA1 ^Vton
V_REGUL
+
R1
−
C1
S3
IN1
S1
SKIP
OFF
OVP
−> Vton during (t1+t2)
−> 0 V during t3 (dead−time)
S2
−> Vton*(t1+t2)/T in average
DT
(high during
dead−time)
Figure 56. V_TON Processing Circuit
The integrator OA1 amplifies the error between V_REGUL and
IN1 so that in average, (V_TON*(t1+t2)/T) equates V_REGUL.
http://onsemi.com
19