NCP1336A Datasheet, PDF (19/26 Pages) ON Semiconductor – Quasi-Resonant Current Mode Controller for High Power Universal Off-Line Supplies

NCP1336A/B
Short−circuit or Overload Mode
Figure 18 shows the implementation of the fault timer.
When the current in the MOSFET is higher than, “Max
(0.8 V / R_sense) Ip” comparator trips and the timer capacitor is
charged by ItimerC current source. When the current comes
back within safe limits, “Max Ip” comparator becomes silent
and the PWM comparator triggers the discharge of the timer
capacitor.
If “IpFlag” and PWMreset occur at the same time, the
PWMreset signal is the strongest and the capacitor is
discharged.
3 ^v(ipflag:x1) 4 ^v(pwm:x1) 8 ^feedback 9 ^vtimer
3.40
1.40
3.00
1.00
2.60 600m
2.20 200m
1.80 −200m
V_FB
89
V_Timer
high
IpFlag
low
high
3
PWMreset
low
4
6.13m
6.37m
6.60m
6.84m
7.08m
time in seconds
Figure 19. Timer Operating Chronograms
There can be various events that force a fault on the
primary side controller. We can split them in different
situation, each having a particular configuration:
1. The converter regulates but the auxiliary winding
collapses: this is a typical situation linked to the
usage of a constant−current / constant−voltage
(CC−CV) type of controller. If the output current
increases, the voltage feedback loop gives up and
the current loop takes over. It means that V_OUT
goes low but the feedback loop is still closed
because of the output current monitoring.
Therefore, seen from the primary side, there is no
fault. However, there are numerous charger
applications where the output voltage shall not go
below a certain limit, even if the current is
controlled. To cope with this situation, the
controller features a precise under−voltage lockout
comparator biased to a VCC_min level. When this
level is crossed, whatever the other pin conditions,
pulses are stopped and the controller enters the
safe hiccup mode, trying to re−start. Figure 20
shows how the converter will behave in this
situation. If the fault goes away, the SMPS
resumes operation.
2. In the second case, the converter operates in
regulation, but the output is severely overloaded.
However, due to the bad coupling between the
power and the auxiliary windings, the controller
V_CC does not go low. The peak current is pushed
to the maximum, the error flag IpFlag is
consequently asserted and the timer starts to count.
Upon completion, all pulses are stopped and
triple−startup hiccup mode is entered for
version B. If the fault goes away, the SMPS
resumes operation (Figure 21). For version A,
when the timer finishes counting, the pulses stop
and the circuit stays latched until the user cycles
down the power supply (Figure 22).
3. Another case exists where the short−circuit makes
the auxiliary level go below VCC_min. In that case,
the timer length is truncated and all pulses are
stopped. The triple hiccup fault mode is entered
and the SMPS tries to re−start. When the fault is
removed, the SMPS resumes operation.
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