NB3N1900K_16 Datasheet, PDF (19/21 Pages) ON Semiconductor – Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe

NB3N1900K
L1
L2
Rs
L1’
L2’
HCSL Output Buffer
Rs
Rt
L4
L4’
Rt
PCI Express
Add−in Board
REF_CLK Input
L3’ L3
Figure 7. PCI Express Connector Routing
Table 32. ALTERNATIVE TERMINATION FOR LVDS AND OTHER COMMON DIFFERENTIAL SIGNALS (Figure 8)
Vdiff (V)
Vpp (V)
Vcm (V)
R1 (W)
R2 (W)
R3 (W)
R4 (W)
Note
0.45
0.22
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
L1
L1’
HCSL Output Buffer
L2
R1a
R3
L4
L4’
L2’
R1b
R2a
R2b
L3’
L3
R4
Down Device
REF_CLK Input
Figure 8. Alternate Termination for LVDS
Table 33. CABLE CONNECTED AC COUPLED APPLICATION (Figure 9)
Component
Value
Note
R5a, R5b
8.2k 5%
R6a, R6b
1k 5%
Cc
0.1 mF
Vcm
0.350 V
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