NCV8702_13 Datasheet, PDF (17/20 Pages) ON Semiconductor – 200 mA, Ultra-Low Quiescent Current, Ultra-Low Noise, LDO Linear Voltage Regulator

NCV8702
400
0.8
350
0.7
P_D(MAX), T_A = 25C, 2 OZ CU
300
0.6
250
0.5
P_D(MAX), T_A = 25C, 1 OZ CU
200
0.4
q_JA, 1 OZ CU
150
0.3
100
q_JA, 2 OZ CU _0.2
50
0.1
0 100 200 300 400 500 600 700 800
PCB COPPER AREA (mm²)
Figure 63. q_JA and P_D(MAX) vs. Copper Area (XDFN6)
Load Regulation
The NCV8702 features very good load regulation of
maximum 2.6 mV in the 0 mA to 200 mA range. In order to
achieve this very good load regulation a special attention to
PCB design is necessary. The trace resistance from the OUT
pin to the point of load can easily approach 100 m which
will cause a 20 mV voltage drop at full load current,
deteriorating the excellent load regulation.
Line Regulation
The IC features very good line regulation of 0.44 mV/V
measured from V_IN = V_OUT + 0.3 V to 5.5 V. For battery
operated applications it may be important that the line
regulation from V_IN = V_OUT + 0.3 V up to 4.5 V is only
0.29 mV/V.
Power Supply Rejection Ratio
The NCV8702 features very good Power Supply
Rejection ratio. If desired the PSRR at higher frequencies in
the range 100 kHz – 10 MHz can be tuned by the selection
of C_OUT capacitor and proper PCB layout.
Output Noise
The IC is designed for ultra−low noise output voltage.
Figures 3 – 8 illustrate the noise performance for different
V_OUT, I_OUT, C_OUT. Generally the noise performance in the
indicated frequency range improves with increasing output
current, although even at I_OUT = 1 mA the noise levels are
below 22 mV_RMS.
Turn−On Time
The turn−on time is defined as the time period from EN
assertion to the point in which V_OUT will reach 98% of its
nominal value. This time is dependent on V_OUT(NOM),
C_OUT, T_A. The turn−on time temperature dependence is
shown below:
400
360
V_OUT = 3.3 V
320
280
240
V_OUT = 0.8 V
200
V_OUT = 1.8 V
160
120
80
40
0
−40 −20 0
V_IN = V_OUT + 0.3 V or 2 V
I_OUT = 10 mA
C_IN = C_OUT = 1 mF
V_EN = 0 V −> 0.9 V
20 40 60 80 100 120 140
T_J, JUNCTION TEMPERATURE (C)
Figure 64. Turn−On Time vs. Temperature
Internal Soft­Start
The Internal Soft−Start circuitry will limit the inrush
current during the LDO turn-on phase. Please refer to
Figure 43 for typical inrush current values for given output
capacitance.
The soft−start function prevents from any output voltage
overshoots and assures monotonic ramp-up of the output
voltage.
PCB Layout Recommendations
To obtain good transient performance and good regulation
characteristics place C_IN and C_OUT capacitors close to the
device pins and make the PCB traces wide. In order to
minimize the solution size use 0402 capacitors. Larger
copper area connected to the pins will also improve the
device thermal resistance. The actual power dissipation can
be calculated by the formula given in Equation 2.
http://onsemi.com
17