LC87F1HC8AUWA-2H Datasheet, PDF (17/27 Pages) ON Semiconductor – 8-bit 1-chip Microcontroller with USB-host controller

LC87F1HC8A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Frequency
Symbol
tSCK(5)
Pin/
Remarks
SCK4(P24)
Conditions
See Fig. 8.
Specification
VDD[V]
min
typ
max
unit
2
Low level
tSCKL(5)
1
pulse width
High level
tSCKH(5)
1
pulse width
tSCKHA(5a)
• USB, SIO0 continuous transfer
mode, AIF, SIO9, and DMCOPY
not used at the same time.
4
• See Fig. 8.
• (Note 4-3-2)
tSCKHA(5b)
tSCKHA(5c)
• USB used at the same time
• SIO0 continuous transfer mode,
2.7 to 5.5
AIF, SIO9, DMCOPY not used at
7
the same time.
• See Fig. 8.
• (Note 4-3-2)
• USB, SIO0 continuous transfer
tCYC
mode, SIO9,
and DMCOPY used at the same
time.
12
• AIF not used at the same time.
• See Fig. 8.
• (Note 4-3-2)
Frequency
Low level
pulse width
High level
pulse width
(Note 4-3-3)
tSCK(6)
tSCKL(6)
tSCKH(6)
SCK4(P24)
• When CMOS output type is
selected.
• See Fig. 8.
tSCKHA(6a)
• USB, SIO0 continuous transfer
mode, AIF, SIO9, and
DMCOPY not used at the same
4/3
1/2
1/2
tSCK
tSCKH(6)
tSCKH(6)
time.
• When CMOS output type is
selected.
• See Fig. 8.
+
(5/3)tCYC
+
(10/3)tCYC
tSCKHA(6b)
• USB used at the same time.
• SIO0 continuous transfer mode,
AIF, SIO9, and DMCOPY not
2.7 to 5.5
tSCKH(6)
tSCKH(6)
used at the same time.
• When CMOS output type is
selected.
• See Fig. 8.
+
(5/3)tCYC
+
(19/3)tCYC
tCYC
tSCKHA(6c)
• USB, SIO0 continuous transfer
mode, SIO9, and DMCOPY used
at the same time.
tSCKH(6)
tSCKH(6)
• AIF not used at the same time.
+
+
• When CMOS output type is
(5/3)tCYC
(34/3)tCYC
selected.
• See Fig. 8.
Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period
from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must
be longer than tSCKHA.
Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following
conditions:
Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V
Continued on next page.
No.A0956-17/27