NCP1271P100G Datasheet, PDF (16/21 Pages) ON Semiconductor – Soft-Skip Mode Standby PWM Controller with Adjustable Skip Level and External Latch

NCP1271
Recover from Standby
In the event that a large load is encountered during skip
cycle operation, the circuit automatically disables the
normal Soft−Skip procedure and delivers maximum power
to the load (Figure 37). This feature, the Transient Load
Detector (TLD), is initiated anytime a skip event is exited
and the FB pin is greater than 2.85 V, as would be the case
for a sudden increase in output load.
output voltage
300 ms max
load current
VFB
V _TLD
Maximum current available
when TLD level is hit
Vskip
ID
Figure 37. Transient Response from Standby
External Latchoff Shutdown
When the Skip/Latch input (Pin 1) is pulled higher than
V_latch (8.0 V typical), the drive output is latched off until
V_CC drops below V_CC(reset) (4.0 V_typical). If Vbulk stays
above approximately 30 Vdc, then the HV FET ensure that
V_CC remains above V_CC(latch) (5.8 V_typical). Therefore, the
controller is reset by unplugging the power supply from the
wall and allowing V_bulk to discharge. Figure 38 illustrates
the timing diagram of V_CC in the latchoff condition.
Startup current source is
charging the V_CC capacitor
12.6 V
Startup current source is
off when V_CC is 12.6 V
5.8 V
Startup current source turns
on when V_CC reaches 5.8 V_CC
Figure 38. Latchoff V_CC Timing Diagram
Figure 39 defines the different voltage regions of the
Skip/latch Pin (Pin 1) operation.
1. When the voltage is above V_latch (7.1 V min,
8.7 V max), the circuit is in latchoff and all drive
pulses are disabled until V_CC cycles below 4.0 V
(typical).
2. When the voltage is between V_{skip−reset} (5.0 V
min, 6.5 V max) and V_latch, the pin is considered
to be opened. The skip level V_skip is restored to
the default 1.2 V.
3. When the voltage is between about 3.0 V and
V_{skip−reset}, the V_skip level is above the normal
operating range of the feedback pin. Therefore,
the output does not switch.
4. When the voltage is between 0 V and 3.0 V, the
V_skip is within the operating range of the
feedback pin. Then the voltage on this pin sets
the skip level as explained earlier.
V _pin1
10 V (max limit)
Output is latched off here.
8V (V_latch)
Pin 1 considered to be opened.
V_skip is reset to default level 1.2 V.
5.7 V (V_{skip−reset} )
Output always low (skipped) here.
3.0 V (always skip)
Adjustable V_skip range.
0 V (no skip)
Figure 39. NCP1271 Pin 1 Operating Regions
The external latch feature allows the circuit designers to
implement different kinds of latching protection. The
NCP1271 applications note (AND8242/D) details several
simple circuits to implement overtemperature protection
(OTP) and overvoltage protection (OVP).
In order to prevent unexpected latchoff due to noise,
it is very important to put a noise decoupling capacitor
near Pin 1 to increase the noise immunity. It is also
recommended to always have a resistor from pin 1 to GND.
This further reduces the risk of premature latchoff. Also
note that if the additional latch−off circuitry has leakage,
it will modify the skip adjust setup.
External Non−Latched Shutdown
Figure 40 illustrates the Feedback (pin 2) operation. An
external non−latched shutdown can be easily implemented
by simply pulling FB below the skip level. This is an
inherent feature from the standby skip operation. Hence, it
allows the designer to implement additional non−latched
shutdown protection.
The device can also be shutdown by pulling the V_CC pin
to GND (<190 mV). In addition to shutting off the output,
this method also places the part into a low current
consumption state.
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