NCP1219 Datasheet, PDF (16/20 Pages) ON Semiconductor – PWM Controller with Adjustable Skip Level and External Latch Input

NCP1219
Oscillator Frequency
6 ms
F_OSC + 7.5%
F_OSC
F_OSC − 7.5%
time
Figure 34. Oscillator Frequency Modulation
Gate Drive
The output drive of the NCP1219 is designed to directly
drive the gate of an n−channel power MOSFET. The DRV
pin is capable of sourcing 500 mA and sinking 800 mA of
drive current. It has typical rise and fall times of 30 ns and
20 ns, respectively, driving a 1 nF capacitive load.
The power dissipation of the output stage while driving
the capacitance of the power MOSFET must be considered
when calculating the NCP1219 power dissipation. The
driver power dissipation can be calculated using
Equation 8,
P_DRV + f_OSC @ Q_G @ V_CC
(eq. 8)
where Q_G is the gate charge of the power MOSFET.
External Latch Input
Board level protection functionality is often
incorporated using external circuits to suit a specific
application. An external fault condition can be used to
disable the controller by bringing the voltage on the
Skip/latch pin above the latch threshold, V_latch (3.9 V
typical). When an external fault condition is detected, the
DRV signal is stopped, and the controller enters low current
operation mode. The external capacitor C_CC discharges
and V_CC drops until V_CC(hiccup) is reached. The high
voltage startup circuit turns on and I_start charges C_CC until
V_CC(on) is reached. V_CC cycles between V_CC(on) and
V_CC(hiccup) until V_CC reaches V_CC(reset). Voltage must be
removed from the HV pin, disabling the startup current and
allowing C_CC to discharge to V_CC(reset). Therefore, the
controller is reset by unplugging the power supply from the
wall to allow V_bulk to discharge. Figure 35 illustrates the
timing diagram of V_CC in the latch−off condition.
Startup current source is
charging the V_CCcapacitor
V_CC(on)
Startup current source is
off when V CC is V_CC(on)
V_CC(hiccup)
Startup current source turns
on when V_CC reaches V_CC(hiccup)
time
Figure 35. Latch−off V_CC Timing Diagram
The external latch feature allows the circuit designers to
implement different kinds of latching protection. Figure 36
shows an example circuit in which a bipolar transistor is
used to pull the Skip/latch pin above the latch threshold.
The R_LIM value is chosen to prevent the Skip/latch pin from
exceeding the maximum rated voltage. The NCP1219
applications note (AND8393/D) details several simple
circuits to implement overtemperature protection (OTP)
and overvoltage protection (OVP).
V_CC
R_LIM
Fault
output
C_skip R_skip
Skip/latch HV
FB
CS
VCC
GND DRV
NCP1219
Figure 36. Circuit Example of an External
Latch−off Circuit
An internal blanking filter prevents fast voltage spikes
caused by noise from latching the part. However, it is
recommended that an external filter capacitor be placed as
close as possible to the Skip/latch pin to further improve the
noise immunity.
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