NCP1124 Datasheet, PDF (16/18 Pages) ON Semiconductor – High Voltage Switcher

NCP1124, NCP1126, NCP1129
Adjustable Ramp Compensation
The NCP112x also include an internal ramp
compensation signal. This is the buffered oscillator clock
delivered during the on time only. Its amplitude V_ramp is
around 2.5 V at maximum duty−cycle. Ramp compensation
is a well−known method used to eliminate the sub−harmonic
oscillations in CCM peak current mode converters. These
oscillations take place at half the switching frequency and
occur only during Continuous Conduction Mode (CCM)
with a duty−ratio greater than 50%. To lower the current
loop gain, one usually mixes between 50% and 100% of the
inductor downslope with the current−sense signal.
Figure 45 depicts how internally the ramp is generated. Note
that the ramp signal will be disconnected from the CS pin,
during the off−time.
In the NCP112x switchers, the oscillator ramp exhibits a
V_ramp 2.5 V swing reached at its maximum duty−ratio. If the
clock operates at a 65−kHz frequency, then the slope of the
ramp is equal to:
S_ramp
+
V_ramp
D_maxT_sw
(eq. 6)
The off−time primary current slope S_p is thus given by
Equation 7:
ǒ Ǔ _{Sp +}
V_out ) V_f
L_p
N_p
N_s
(eq. 7)
Given a sense resistor R_sense the above current ramp turns
into a voltage ramp of the following amplitude:
S_sense + S_pR_sense
(eq. 8)
The slope of compensation ramp is chosen to be the same
as the downslope of the sensing ramp for better transient
response. The internal resistor connected to the
compensation ramp is 20 kW. The series compensation
resistor value is therefore:
R_comp
+
R_ramp
S_sense
S_ramp
(eq. 9)
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. A100 pF capacitor is
recommended to be added to the current sense pin to the
switcher ground for improved noise immunity with the
current sensing components located very close to the
switcher.
Figure 45. Internal Adjustable Ramp
Compensation Architecture
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