LC87FBH08A_16 Datasheet, PDF (16/32 Pages) ON Semiconductor – 8-bit Microcontroller

LC87FBH08A
Allowable Operating Conditions at Ta = 40C to +85C, VSS1 = VSS2 = 0V
Parameter
Symbol
Operating
supply voltage
(Note 2-1)
Memory
sustaining
supply voltage
High level
input voltage
Low level
input voltage
VDD(1)
VDD(2)
VDD(3)
VHD
VIH(1)
VIH(2)
VIH(3)
VIL(1)
VIL(2)
High level
output current
VIL(3)
IOH(1)
IOH(2)
IOH(3)
IOH(4)
IOH(5)
IOH(6)
Pin/Remarks
VDD1
VDD1
Conditions
0.245s  tCYC  200s
0.294s  tCYC  200s
0.735s  tCYC  200s
RAM and register contents sustained
in HOLD mode.
VDD[V]
Specification
min
typ
max
unit
2.7
5.5
2.2
5.5
1.8
5.5
1.6
Ports 1, 2, 3, 7
Ports 0
CF1, CF2, RES
Ports 1, 2, 3, 7
Ports 0
CF1, CF2, RES
Ports 0, 1, 2,
P71 to P73
Per 1 applicable pin
Ports 3,
P05 (System clock
output function
used)
Per 1 applicable pin
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
4.0 to 5.5
1.8 to 4.0
4.0 to 5.5
1.8 to 4.0
1.8 to 5.5
4.5 to 5.5
0.3VDD+0.7
0.3VDD+0.7
0.75VDD
VSS
VSS
VSS
VSS
VSS
1.0
2.7 to 4.5
0.35
1.8 to 2.7
0.15
4.5 to 5.5
6.0
2.7 to 4.5
1.4
1.8 to 2.7
0.8
VDD
VDD
V
VDD
0.1VDD+0.4
0.2VDD
0.15VDD+0.4
0.2VDD
0.25VDD
IOH(1)
Ports 0, 1, 2, 3, 7 Total of all applicable pins
4.5 to 5.5
25
IOH(2)
2.7 to 4.5
11.2
IOH(3)
1.8 to 2.7
5.4
Low level
output current
IOL(1)
IOL(2)
Ports 0, 1, 2, 3
Per 1 applicable pin
4.5 to 5.5
2.7 to 4.5
10
1.4 mA
IOL(3)
1.8 to 2.7
0.8
IOL(4)
Port 7, CF2
Per 1 applicable pin
2.7 to 5.5
1.4
IOL(5)
1.8 to 2.7
0.8
IOL(6)
P00, P01
Per 1 applicable pin
4.5 to 5.5
25
IOL(7)
2.7 to 4.5
4
IOL(8)
1.8 to 2.7
2
IOL(1)
Ports 0, 1, 2, 3,
Total of all applicable pins
4.5 to 5.5
70
IOL(2)
CF2
2.7 to 4.5
34.6
IOL(3)
1.8 to 2.7
19.2
IOL(4)
Ports 7
Total of all applicable pins
2.7 to 5.5
5.6
IOL(5)
1.8 to 2.7
3.2
Instruction
cycle time
(Note 2-2)
tCYC
2.7 to 5.5
2.2 to 5.5
1.8 to 5.5
0.245
0.294
0.735
200
200 s
200
External
FEXCF
CF1
 CF2 pin open
system clock
 System clock frequency division
2.7 to 5.5
0.1
12
frequency
ratio=1/1
 External system clock duty=505%
1.8 to 5.5
0.1
 CF2 pin open
3.0 to 5.5
0.2
 System clock frequency division
4
MHz
24.4
ratio=1/2
2.0 to 5.5
0.2
8
 External system clock duty=505%
Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Continued on next page.
www.onsemi.com
16