NCV8851B Datasheet, PDF (15/18 Pages) ON Semiconductor – Automotive Grade Synchronous Buck Controller

NCV8851B
The capacitance itself causes a voltage ripple due to the
current ripple. This is as follows:
V_Q
+
i_L
@
C
D
@ F_SW
Where: v_Q: output voltage ripple due to output capacitance
[Vpp]
Also, the ripple current through the inductor causes a
voltage ripple over the output capacitor due to its ESR as
follows:
V_ESR + i_L @ R_ESR
Where: v_ESR: output voltage ripple due to the effects of ESR
[Vpp]
R_ESR: total ESR of output capacitors [W]
Typically, the ripple due to ESR dominates, having the
largest effect on output voltage ripple. The total output
voltage ripple in steady−state operation can be calculated as
follows:
V_OUT + V_Q ) V_ESR + Ë_C @ V_OUT
Where: v_OUT: total output voltage ripple [Vpp]
κ_C: percent output voltage ripple [%]
Typically, the voltage ripple percentage is a performance
parameter used to decide on the desired output capacitor.
The maximum total effective ESR of the output capacitors
is calculated as follows:
R_ESR(max)
+
V_OUT * V_Q
i_L(max)
Where: R_ESR(max): maximum allowable total ESR of output
capacitors
It should be noted that these values of ESR are at the
switching frequency and ESR decreases as frequency
increases. The steady−state power lost due to the ESR of the
output capacitor can be calculated as follows:
P_C(ESR)
+
1
3
i_L
2
@
R_ESR
(6) Input Capacitor Selection
The input capacitors have to sustain the ripple current
produced during the on time of the high−side MOSFET and
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
I_IN(RMS) + I_OUT ^ǸD @ (1 * D)
Where: I_IN(RMS) = input RMS current
The large majority of the ripple spectrum will be at the
switching frequency. The above equation reaches its
maximum value with D = 0.5, I_IN(RMS) = I_OUT/2. The input
capacitors must be rated to handle a ripple current of
one−half the maximum output current at the switching
frequency.
ESR is the majority cause of losses in the input capacitors.
Losses in the input capacitors can be calculated with the
following equation:
P_CIN + I_IN(RMS) ² @ R_ESR(CIN)
Where: P_CIN = power loss in the input capacitors
R_ESR(CIN) = effective series resistance of the input
capacitance
Due to large current transients through the input
capacitors, electrolytic, polymer or ceramics should be used.
If a tantalum must be used, it must be surge protected, to
prevent against capacitor failure. Due to the large ripple
current, it is common to put small ceramic capacitors in
parallel with the bulk input capacitors, which will handle a
significant portion of the ripple current. A value of 0.01 mF
to 0.1 mF placed near the MOSFETs is recommended.
(7) Compensator Design
The purpose of the compensators is to stabilize the
dynamic response of the converter. By optimizing the
compensators, stable regulation with fast input line and
output load transient response is achieved.
Compensator design is related to the placement of zeros
and poles in the closed loop, in order to assure stability with
optimized transient response. The general approach is to use
some rule of thumb values and then tune them through
simulation to optimize load step response, while assuring
stability over line and load variations.
Type−II compensators are used with the two error
amplifiers in average current mode control. The CEA closes
the inner current−loop and the VEA closes the outer
voltage−loop. As a rule of thumb, a zero is placed in each
loop with the intent to compensate the effects of the double
pole from the output inductor and capacitor. Additionally, a
pole is placed at origin, due to the negative feedback, and a
pole is also placed in each loop with the intent to compensate
the effects of the double right−half−plane zero from the
current sampling function.
The crossover frequency is then set so that gain limitations
of the error amplifier are not exceeded. The compensator
must assure there is adequate phase margin in the total
closed−loop response, which can be analyzed on a
small−signal basis. Further reduction in loop gain, via
decreasing the crossover frequency, may be required to
avoid large−signal clamping limitations; this effect can be
seen in simulation and taken care of in the compensator
tuning process.
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