NCT80 Datasheet, PDF (15/28 Pages) ON Semiconductor – Hardware Monitor with I2C Serial Interface

NCT80
FAN_DIVISOR_OUTPUT_PIN_CONFIG
Register Information
Description
This register allows the user to configure the TACH reading modes and also the OS and RST_OUT
pin configuration.
Offset
0x05
Bitfield Details
Field
Name
Description
Access Default
7
RST_en
Setting this bit to 1 enables the RST_OUT functionality on the RST_OUT / OS
RW
0
output pin. If bits 6 and 7 are set to 0 then this pin is disabled.
6
OS_pin_en
Setting this bit to 1 enables the OS functionality on the RST_OUT / OS output
RW
0
pin. For the OS pin to function, bit 7 of this register must be set to 0. If bits 6
and 7 are set to 0 then this pin is disabled.
5:4
TACH2_divisor If level sensitive input is selected setting bit <4> = 1 selects and active−low
input (An interrupt will be generated if the TACH2 input is Low), if bit <4> = 0
selects an active−high input (an interrupt will be generated if the TACH2
input is High).
RW
0x1
0x0:
Divide by 1
0x1:
Divide by 2
0x2:
Divide by 4
0x3:
Divide by 8
3:2
TACH1_divisor If level sensitive input is selected setting bit <2> = 1 selects and active−low
input (An interrupt will be generated if the TACH1 input is Low), if bit <2> = 0
selects an active−high input (an interrupt will be generated if the TACH1 input
is High).
RW
0x1
0x0:
Divide by 1
0x1:
Divide by 2
0x2:
Divide by 4
0x3:
Divide by 8
1
TACH2_mode Setting this bit to 1 selects the level sensitive input mode.
Setting this bit to 0 selects TACH Count Mode for the input pin.
RW
0
0
TACH1_mode Setting this bit to 1 selects the level sensitive input mode.
Setting this bit to 0 selects TACH Count Mode for the input pin.
RW
0
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