NCP706_16 Datasheet, PDF (15/16 Pages) ON Semiconductor – Precision Very Low Dropout Voltage Regulator with Enable

NCP706
APPLICATIONS INFORMATION
Input Decoupling (Cin)
A 4.7 mF capacitor either ceramic or tantalum is
recommended and should be connected as close as possible
to the pins of NCP706 device. Higher values and lower ESR
will improve the overall line transient response.
Output Decoupling (Cout)
The minimum decoupling value for NCP706MX21TAG
and NCP706MX22TAG devices is 4.7 mF and can be
augmented to fulfill stringent load transient requirements.
The minimum decoupling value for NCP706MX295TAG
and NCP706MX706300TAG devices is 1 mF. The regulator
accepts ceramic chip capacitors MLCC. If a tantalum
capacitor is used, and its ESR is large, the loop oscillation
may result. Larger values improve noise rejection and
PSRR.
Enable Operation
The enable pin EN will turn on or off the regulator. These
limits of threshold are covered in the electrical specification
section of this data sheet. If the enable is not used then the
pin should be connected to V_IN.
Hints
Please be sure the V_in and GND lines are sufficiently wide.
If their impedance is high, noise pickup or unstable
operation may result.
Set external components, especially the output capacitor,
as close as possible to the circuit.
The sense pin SNS trace is recommended to be kept as far
from noisy power traces as possible and as close to load as
possible.
Thermal
As power across the NCP706 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature affect the rate of temperature rise for the part.
This is stating that when the NCP706 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation.
The power dissipation across the device can be roughly
represented by the equation:
P_D + ^ǒV_IN * V_OUT^Ǔ * I_OUT [W]
(eq. 1)
The maximum power dissipation depends on the thermal
resistance of the case and circuit board, the temperature
differential between the junction and ambient, PCB
orientation and the rate of air flow.
The maximum allowable power dissipation can be
calculated using the following equation:
P_MAX + ^ǒT_J * T_A^Ǔńq_JA [W]
(eq. 2)
Where (T_J − T_A) is the temperature differential between
the junction and the surrounding environment and q_JA is the
thermal resistance from the junction to the ambient.
Connecting the exposed pad and non connected pin 3 to
a large ground pad or plane helps to conduct away heat and
improves thermal relief.
ORDERING INFORMATION
Device
Nominal Ooutput
Voltage
Marking
Package
Shipping^†
NCP706MX21TAG
2.1 V
QM
XDFN8
(Pb−Free)
3000 / Tape & Reel
NCP706MX22TAG
2.2 V
QR
XDFN8
(Pb−Free)
3000 / Tape & Reel
NCP706MX295TAG
2.95 V
A2
XDFN8
3000 / Tape & Reel
(Pb−Free)
NCP706MX300TAG
3.0 V
A3
XDFN8
3000 / Tape & Reel
(Pb−Free)
NCP706MX33TAG
(In Development)
3.3 V
Q3
XDFN8
3000 / Tape & Reel
(Pb−Free)
(Available Soon)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
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