NCP5425 Datasheet, PDF (15/22 Pages) ON Semiconductor – Dual Synchronous Buck Controller

NCP5425
Maximum allowable ESR can then be determined
according to the formula:
ESRMAX
+
DVESR
DIOUT
where:
DV_ESR =change in output voltage due to ESR
(assigned by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be calculated:
Number
of
capacitors
+
ESRCAP
ESRMAX
where:
ESR_CAP = maximum ESR per capacitor
(specified in manufacturer’s data sheet);
ESR_MAX = maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
DVESR + DIOUT ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESLMAX
+
DVESL
DI
Dt
Input Inductor Selection
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors during power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. An input inductor successfully blocks the ripple
current while placing the transient current requirements on
the input bypass capacitor bank, which has to initially
support the sudden load change. The minimum value for the
input inductor is:
LIN
+
DV
(dlńdt)MAX
where:
L_IN = input inductor value;
DV = voltage seen by the input inductor during a full load
swing;
(dI/dt)_MAX = maximum allowable input current slew rate.
The designer must select the LC filter pole frequency such
that a minimum of 40 dB attenuation is obtained at the
regulator switching frequency. The LC filter is a
double−pole network with a slope of −2.0, a roll−off rate of
−40 dB/decade, and a corner frequency given by:
fC +
2p
1
Ǹ_LC
where:
L = input inductor;
C = input capacitor(s).
POWER FET SELECTION
FET Basics
The use of a MOSFET as a power switch is compelled by
two reasons: 1) high input impedance; and 2) fast switching
times. The electrical characteristics of a MOSFET are
considered to be nearly those of a perfect switch. Control
and drive circuitry power is therefore reduced. Because the
input impedance is so high, it is voltage driven. The input of
the MOSFET acts as if it were a small capacitor, which the
driving circuit must charge at turn on. The lower the drive
impedance, the higher the rate of rise of V_GS, and the faster
the turn−on time. Power dissipation in the switching
MOSFET consists of: (1) conduction losses, (2) leakage
losses, (3) turn−on switching losses, (4) turn−off switching
losses, and (5) gate−transitions losses. The latter three losses
are all proportional to frequency. The most important aspect
of FET performance is the Static Drain−to−Source
On−Resistance (R_DS(ON)), which affects regulator
efficiency and FET thermal management requirements. The
On−Resistance determines the amount of current a FET can
handle without excessive power dissipation that may cause
overheating and potentially catastrophic failure. As the
drain current rises, especially above the continuous rating,
the On−Resistance also increases. Its positive temperature
coefficient is between +0.6%/_C and +0.85%/_C. The
higher the On−Resistance, the larger the conduction loss is.
Additionally, the FET gate charge should be low in order to
minimize switching losses and reduce power dissipation.
Both logic level and standard FETs can be used. Voltage
applied to the FET gates depends on the application circuit
used. Both upper and lower gate driver outputs are specified
to drive to within 1.5 V of ground when in the low state and
to within 2.0 V of their respective bias supplies when in the
high state. In practice, the FET gates will be driven
rail−to−rail due to overshoot caused by the capacitive load
they present to the controller IC.
Switching (Upper) FET Selection
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150_C. The maximum RMS
current through the switch can be determined by the
following formula:
Ǹ _{IRMS(H) +}
ƪ_{IL(PEAK)2 ) (IL(PEAK)}
IL(VALLEY)) ) IL(VALLEY)2
3
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