AX5031_16 Datasheet, PDF (15/22 Pages) ON Semiconductor – Advanced Multi-channel Single Chip UHF Transmitter

AX5031
REGISTER BANK DESCRIPTION
This section describes the bits of the register bank in
detail. The registers are grouped by functional block to
facilitate programming.
No checks are made whether the programmed
combination of bits makes sense! Bit 0 is always the LSB.
NOTES: Whole registers or register bits marked as
reserved should be kept at their default values.
All addresses not documented here must not be
accessed, neither in reading nor in writing.
Table 17. CONTROL REGISTER MAP
Bit
Addr
Name
Dir Reset
7
6
5
4
3
2
1
0
Description
Revision & Interface Probing
0 REVISION
R 00100001 SILICONREV(7:0)
Silicon Revision
1 SCRATCH
RW 11000101 SCRATCH(7:0)
Scratch Register
Operating Mode
2 PWRMODE
RW 011−0000 RST
REFEN XOEN −
PWRMODE(3:0)
Power Mode
Crystal Oscillator, Part 1
3 XTALOSC
RW −−−−0010 −
−
−
−
XTALOSCGM(3:0)
GM of Crystal Oscillator
FIFO, Part 1
4 FIFOCTRL
RW −−−−−−11 FIFOSTAT(1:0)
FIFO FIFO
FIFO
OVER UNDER FULL
FIFO
FIFOCMD(1:0) FIFO Control
EMPTY
5 FIFODATA
RW −−−−−−−− FIFODATA(7:0)
FIFO Data
Interrupt Control
6 IRQMASK
RW −0000000 −
IRQMASK(6:0)
IRQ Mask
7 IRQREQUEST R −−−−−−−− −
IRQREQUEST(6:0)
IRQ Request
Interface & Pin Control
0C PINCFG1
RW 00101000 −
IRQZ −
SYSCLK(3:0)
Pin Configuration 1
0D PINCFG2
RW 00000000 −
IRQE −
−
IRQI −
Pin Configuration 2
0E PINCFG3
RW 0−−−−−−− reserved −
−
SYSCLKR −
IRQR −
Pin Configuration 3
0F IRQINVERSION RW −0000000 −
IRQINVERSION(6:0)
IRQ Inversion
Modulation & Framing
10 MODULATION RW −0000010 −
MODULATION(6:0)
Modulation
11 ENCODING
RW −−−00010 −
−
−
ENC
ENC
ENC
ENC ENC Encoder/Decoder
NOSYNC MANCH SCRAM DIFF INV Settings
12 FRAMING
RW −0000000 −
HSUPP CRCMODE(1:0)
FRMMODE(2:0)
−
Framing settings
14 CRCINIT3
RW 11111111 CRCINIT(31:24)
CRC Initialization Data or
Preamble
15 CRCINIT2
RW 11111111 CRCINIT(23:16)
CRC Initialization Data or
Preamble
16 CRCINIT1
RW 11111111 CRCINIT(15:8)
CRC Initialization Data or
Preamble
17 CRCINIT0
RW 11111111 CRCINIT(7:0)
CRC Initialization Data or
Preamble
Voltage Regulator
1B VREG
R −−−−−−−− −
−
−
−
SSDS SSREG SDS
SREG Voltage Regulator Status
Synthesizer
1C FREQB3
1D FREQB2
1E FREQB1
1F FREQB0
RW 00111001
RW 00110100
RW 11001100
RW 11001101
FREQB(31:24)
FREQB(23:16)
FREQB(15:8)
FREQB(7:0)
2^nd Synthesizer Frequency
2^nd Synthesizer Frequency
2^nd Synthesizer Frequency
2^nd Synthesizer Frequency
20 FREQ3
RW 00111001 FREQ(31:24)
Synthesizer Frequency
21 FREQ2
RW 00110100 FREQ(23:16)
Synthesizer Frequency
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