NCP1578 Datasheet, PDF (14/22 Pages) ON Semiconductor – Synchronous Step-Down Controller with 50 mA Linear Regulator

NCP1578
SMPS is disabled by EN_SW. Note that the PGOOD pin is
valid providing LDO5 is high enough to maintain the
internal logic state.
Overvoltage Protection
When SMPS output voltage is above 115% (typ) the
preset nominal regulation voltage for 16 consecutive
internal clock cycles, the SMPS output will be latch off and
it can be restarted by toggling EN_SW or LDO5.
Undervoltage Protection
When SMPS output falls below 65% (typ) of the nominal
regulation voltage for 16 consecutive internal clock cycles,
the undervoltage fault is set, the SMPS is latched off.
Cycling EN_SW or LDO5 can reset the undervoltage fault
latch and restart the controller.
Soft-Start
The switcher V_OUT soft-start feature is incorporated in
the device to prevent surge current from power supply and
output voltage overshot during power up. When EN_SW,
LDO5 rises above their respective upper threshold voltages,
the external soft start capacitor C_ss is charged by a constant
current source I_ss. When the soft-start voltage reaches the
V_ref voltage, the soft start process is finished. The soft-start
time Tss can be programmed by the soft-start capacitor
according to the following equation: T_ss [ (0.8 x C_ss) / I_ss.
OPERATION TABLE 1 (Single Supply V_BAT Configuration)
Input Condition
Operating Condition
FPWM EN_LDO EN_SW
SMPS
X
Low
X
Off
X
High
Low
Off
High
High
High
On (FPWM)
Low
High
High
On (DCM or Pulse Skipping)
LDO5
Off
On
On
On
Output Condition
PGOOD
H-Z
Low
H-Z
H-Z
OPERATION TABLE 2 (External +5 V and V_IN Configuration (Note 4))
Input Condition
Operating Condition
FPWM
EN_LDO
(Note 5)
EN_SW
SMPS
X
Low
Low
Off
High
Low
High
On (FPWM)
Low
Low
High
On (DCM or pulse skipping)
4. External +5 V is connecting to V_BAT and LDO5 pin.
5. For this configuration, it is recommended to pull EN_LDO to GND at any time.
Output Condition
PGOOD
Low
H-Z
H-Z
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