NCP1217A_15 Datasheet, PDF (14/19 Pages) ON Semiconductor – Enhanced PWM Current-Mode Controller for High-Power Universal Off-Line Supplies

NCP1217, NCP1217A
ON/OFF
1
8
2
7
3
6
Q1
4
5
Figure 26. Another Way of Shutting Down the IC
Without a Definitive Latchoff State
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between V_CC and GND. If the current sense pin is
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its V_CC capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
coefficient Q of the resonating network formed by Lp and
Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge (Q = I * t) immediately
latches the controller that brutally discharges its V_CC
capacitor. If this V_CC capacitor is of sufficient value, its
stored energy damages the controller. Figure 27 depicts a
typical negative shot occurring on the HV pin where the
brutal V_CC discharge testifies for latchup.
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