LV5685PV Datasheet, PDF (14/29 Pages) ON Semiconductor – System Power Supply IC for Automotive Infotainment Multiple-Output Linear Voltage Regulator

LV5685PV
I²C bus interface format (MSB first)
This part is I²C controlled power supply, using 2 wires of SCL,SDA.
The communication protocol comprises start-condition, device-address, sub-address, data and stop-condition.
Every 8bits are followed by ACK bit, and the receiver device pulls down SDA line during ACK period.
This part doesn't accept sub-address auto increment format. (Single data byte write per a communication.)
The protocol in Read-mode comprises start-condition, device-address, data1, data2 and stop-condition.
(Note)The I²C-bus communication may be unstable when VDD voltage is not stable or out of specification range, since
I²C-BUS circuitry is supplied by VDD.
Write mode
SCL
SDA
Start
Condition
S6 S5 S4 S3 S2 S1 S0 W AK A7 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
Device Address + R/W + ACK
Sub Address(A) + ACK
Data(address A) + ACK
Stop
Condition
Read mode
SCL
SDA
Start
Condition
S6 S5 S4 S3 S2 S1 S0 R AK D15 D14 D13 D12 D11 D10 D9 D8 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
Device Address + R/W + ACK
Read data1 + ACK
Read data2 + ACK
Stop
Condition
• Device address
S6
S5
S4
0
0
0
S3
S2
S1
S0
R/W
1
0
0
0
1/0
• Register map
Write
D7
PM ILM_EN
VCTL ILM_V1
DET ACC_V1
D6
CD_EN
ILM_V0
ACC_V0
D5
AUDIO_EN
CD_V1
UVD_V1
D4
SW33_EN
CD_V0
UVD_V0
D3
EXT_EN
AUD_V1
FLGMD1
D2
ANT_EN
AUD_V0
FLGMD0
D1
SW_V
D0
init
00000000
00000000
00000000
Read
VCTL
D15
ILM_V1
D14
ILM_V0
D13
CD_V1
D12
CD_V0
D11
D10
AUD_V1 AUD_V0
D9
SW_V
D8
init
V6DET 00000000
D7
D6
D5
D4
D3
D2
D1
D0
init
FLG ACCUV
UV
OV
OVP
V6SDN
OC
0
0
00000000
No.A2333-14/29