NCP1217 Datasheet, PDF (13/18 Pages) ON Semiconductor – Enhanced PWM Current-Mode Controller for High-Power Universal Off-Line Supplies

NCP1217, NCP1217A
In normal operation, the Adj pin level is kept at a fixed
level, the default one or lower. As soon as some external
signal pulls this Adj pin level above 3.1 V typical, the output
pulses are permanently disabled. Care must be taken to limit
the injected current into pin 1 to less than 2.0 mA, e.g.
through a series resistor of 5.6 k with a 10 V V_CC. The
startup switch is activated every time V_CC reaches 5.6 V and
maintains a V_CC voltage ramping up and down between
5.6 V and 12.8 V. Reset occurs when V_CC falls below 5.6 V,
e.g. when the user cycle the SMPS down. Figure 25
illustrates the operation. Adding a zener diode from Q1 base
to ground makes a cheap OVP, protecting the supply from
any lethal open−loop operation. If a thermistor (NTC) is
added in parallel with the Zener−diode, overtemperature
protection is also ensured.
Vaux
T
OVP
1
8
2
7 ^{t16 V}
3
6
4
5
CV_CC
Laux
Figure 25. A Thermistor and a Zener Diode Offer
Both OVP and Overtemperature Latched−Off
Protection
Non−Latching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj Pin 1 level, the
output pulses are disabled as long as FB is pulled below
Pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 26 depicts the application example.
ON/OFF
1
8
2
7
3
6
Q1
4
5
Figure 26. Another Way of Shutting Down the IC
Without a Definitive Latchoff State
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between V_CC and GND. If the current sense pin is
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its V_CC capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
coefficient Q of the resonating network formed by Lp and
Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge (Q = I * t) immediately
latches the controller that brutally discharges its V_CC
capacitor. If this V_CC capacitor is of sufficient value, its
stored energy damages the controller. Figure 27 depicts a
typical negative shot occurring on the HV pin where the
brutal V_CC discharge testifies for latchup.
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