NB3W1900L_16 Datasheet, PDF (13/20 Pages) ON Semiconductor – 3.3 V 100/133 MHz Differential 1:19 HCSL-Compatible Push‐Pull Clock ZDB/Fanout Buffer

NB3W1900L
Buffer Power−Up State Machine
Table 19. BUFFER POWER−UP STATE MACHINE
State
Description
0
3.3 V Buffer power off
1
After 3.3 V supply is detected to rise above 3.135 V, the buffer enters State 1 and initiates a 0.1 ms–0.3 ms delay.
2
Buffer waits for a valid clock on the CLK input and PWRDN# de−assertion (or PWRGD assertion low to high)
3
Once the PLL is locked to the CLK_IN input clock, the buffer enters state 3 and enables outputs for normal operation.
(Notes 45, 46)
45. The total power up latency from power on to all outputs active must be less than 1.8 ms (assuming a valid clock is present on CLK_IN input).
46. If power is valid and powerdown is de−asserted (PWRGD asserted) but no input clocks are present on the CLK_IN input, DIF clocks must
remain disabled. Only after valid input clocks are detected, valid power, PWRDN# de−asserted (PWRGD asserted) with the PLL
locked/stable and the DIF outputs enabled.
No input clock
State 1
Delay
0.1 ms − 0.3 ms
State 2
Wait for input
clock and
powerdown
de−assertion
Powerdown Asserted
State 0
Power Off
State 3
Normal
Operation
Figure 4. Buffer Power−Up State Diagram
Device Power−Up Sequence
Follow the power−up sequence below for proper device
functionality:
1. PWRGD/PWRDN# pin must be Low.
2. Assign remaining control pins to their required
state (100M_133M#, HBW_BYPASS_LBW#,
SDA, SCL)
3. Apply power to the device.
4. Once the VDD pin has reached a valid VDDmin
level (3.3V −5%), the PWRGD/PWRDN# pin
must be asserted High. See Figure 5.
Note: If no clock is present on the CLK_IN/CLK_IN#
pins when device is powered up, there will be no clock on
DIF/DIF# outputs.
Figure 5. PWRGD and VDD Relationship Diagram
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