MT9V022 Datasheet, PDF (13/58 Pages) ON Semiconductor – Wide-VGA CMOS Digital Image Sensor

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Output Data Format
Output Data Timing
The data output of the MT9V022 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 7: Timing Example of Pixel Data
LINE_VALID
PIXCLK
Blanking
...
...
Valid Image Data
...
Blanking
DOUT(9:0)
P0
P1
P2
P3
P4 _...
Pn-1
Pn
(9:0)
(9:0)
(9:0)
(9:0)
(9:0)
(9:0)
(9:0)
Figure 8:
The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows
PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled,
the PIXCLK is HIGH for one complete master clock master period and then LOW for one
complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for
two complete master clock periods and then LOW for two complete master clock
periods. It is continuously enabled, even during the blanking period. Setting R0x74
bit[4] = 1 causes the MT9V022 to invert the polarity of the PIXCLK.
The parameters P1, A, Q, and P2 in Figure 8 are defined in Table 2.
Row Timing and FRAME_VALID/LINE_VALID Signals
FRAME_VALID
LINE_VALID
Number of master clocks ^{P1 A}
Q
...
...
...
A
Q
A
P2
Table 2:
Parameter
Frame Time
Name
A
Active data time
P1
Frame start blanking
P2
Frame end blanking
Q
Horizontal blanking
Equation
R0x04
R0x05 - 23
23 (fixed)
R0x05
Default Timing at 26.66 MHz
752 pixel clocks
= 752 master
= 28.20s
71 pixel clocks
= 71master
= 2.66s
23 pixel clocks
= 23 master
= 0.86s
94 pixel clocks
= 94 master
= 3.52s
MT9V022_DS Rev. L 6/15 EN
13
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