NCP81278 Datasheet, PDF (12/13 Pages) ON Semiconductor – Compact 2-Phase Synchronous Buck Controller with Integrated Gate Drivers and PWM VID Interface

NCP81278
LAYOUT GUIDELINES
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction.
• Power Paths: Use wide and short traces for power
paths to reduce parasitic inductance and
high−frequency loop area. It is also good for efficiency
improvement.
• Power Supply Decoupling: The power MOSFET
bridges should be well decoupled by input capacitors
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission. Place decoupling caps as close as
possible to the controller PVCC pin.
• Output Decoupling: The output capacitors should be
as close as possible to the load like a GPU. If the load is
distributed, the capacitors should also be distributed
and generally placed in greater proportion where the
load is more dynamic.
• Switching Nodes: Switching nodes between HS and
LS MOSFETs should be copper pours to carry high
current and dissipate heat, but compact because they are
also noise sources.
• Gate Drive: All the gate drive traces such as HGx,
LGx, PHx, and BSTx should be short, straight as
possible, and not too thin. The bootstrap cap and an
option resistor need to be very close and directly
connected between BSTx pin and PHx pin.
• Ground: It would be good to have separated ground
planes for PGND and GND and connect the two planes
at one point. PGND plane is an isolation plane between
noisy power traces and all the sensitive control circuits.
Directly connect the exposed pad (GND pin) to GND
ground plane through vias. The analog control circuits
should be surrounded by GND ground plane. GND
ground plane is connected to PGND plane by single
joint with low impedance.
• Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
• Current Sense: The NCP81278 senses phase currents
by monitoring voltages from phase nodes PHx to the
common ground GND pin. PGND ground plane should
be well underneath PHx trances. To get better current
balance between the two phases, try to make a layout as
symmetrical as possible and balance the current flow in
PGND plane for the two phases.
• Compensation Network: The compensation network
should be close to the controller. Keep FB trace short to
minimize their capacitance to GND.
• PWM VID Circuit: The PWM VID is a high slew−rate
digital signal from GPU to the controller. The trace
routing of it should be done to avoid noise coupling
from the switching node and to avoid coupling to other
sensitive analog circuit as well. The RC network of the
PWM VID circuit needs to be close to the controller. A
10 nF ceramic cap is connected from VREF pin to
GND plane, and another small ceramic cap is connected
from REFIN pin to GND plane.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small−form factor VR with reduced temperature rise.
• The exposed pads of the controller and power
MOSFETs must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More vias are welcome to be underneath the exposed
pads and surrounding the power devices to connect the
inner ground layers to reduce thermal resistances.
• Use large area copper pour to help thermal conduction
and radiation.
• Try distributing multiple heat sources to reduce
temperature rise in hot spots.
www.onsemi.com
12