NCP81174N Datasheet, PDF (12/18 Pages) ON Semiconductor – 4/3/2-Phase Synchronous Buck Controller

NCP81174N
PWM VID
The NCP81174N receives the PWMVID signal from the
upstream controller for the Vcore regulation. The signal is
decoded internally and passed to the VID buffer output
(VIDBUF), where the duty cycle is converted to a
corresponding signal between 0 V and 2 V. The VIDBUF
high level is derived from a precise 2.0 V reference voltage.
The VIDBUF signal is then filtered through the external low
pass filter constructed by R_REFADJ and C_REFIN. The
filtered output is connected to the REFIN pin. The REFIN
is the voltage reference of the Vcore regulator. The output
voltage maximum, minimum, and also boot voltage can be
calculated with below equations.
R_VREF2
(eq. 2)
V_max + Vref @ _{RVREF2 ) ǒR_VREF1 ø R_REFADJǓ}
R_VREF1 ø R_REFADJ ^{(eq. 3)}
V_min + Vref @ _{R_VREF1 ) ǒR_VREF1 ø R_REFADJǓ}
V_boot
+
V_max
)
2
V_min
(eq. 4)
VREF
PWMVID
VIDBUF
R _REFADJ
R _VREF1
C_ REFIN
R _VREF2
REFIN
Figure 6. PWM VID Interface
Soft Start
The NCP81174N has an internal controlled soft start
function. The output starts to ramp up following a system
reset period after the device is enabled. The device is able to
start up smoothly under an output pre−biased condition
without discharging the output before ramping up.
Before the output soft start begins, an internal switch will
be turned on to discharge the external filter capacitor
C_REFIN connected to the REFIN pin to reset the DAC
setting, the typical on resistance of the switch is around 6 Ws.
After the discharging, internal switch will be turned off to
allow external C_REFIN capacitor to recharge. After ~
100 ms interval, the output voltage ramps up with a fixed
slew rate.
The circuit can be set to start from either all the phases
when the input power rails are all available or from phase 1
when only one input power rail is available by presetting the
power mode from PSI pin (See Power Operation Modes).
Thermal Compensation Amplifier with VDRP and
VDFB Pins
Thermal compensation amplifier is an internal amplifier
in the path of droop current feedback for additional
adjustment of the gain of summing current and temperature
compensation. The way thermal compensation is
implemented separately ensures minimum interference to
the voltage loop compensation network.
PWM Comparators with Hysteresis and 3^rd State of
PWM Outputs
Four PWM comparators receive an error signal at their
non−inverting input and one of the triangle waves at its
inverting input. The output of each comparator generates the
PWM outputs G1, G2, G3 and G4.
During the steady state operation, the duty cycle will
center on the valley of the triangle waveform, with steady
state duty cycle calculated by Vout/Vin. During a transient
event, both high and low comparator output transitions shift
phase to the points where the error signal intersects the down
and up ramp of the triangle wave.
PWM signals vary between high and low in all phase
operation or forced PWM mode. In power saving mode
(PS2), PWM signals vary between high and mid level to
allow diode emulation.
2/3/4 Phase Operation
Besides 4−phase, the part can be configured to run in 2 or
3−phase mode. In 2−phase mode, phase 1 and 3 should be
used to drive the external gate drivers, gate outputs G2 and
G4 should be grounded. In 3−phase mode, gate output G4
should be grounded. The current sense inputs of the unused
channels should be connected to the Vcore output.
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