NCP1593_12 Datasheet, PDF (12/13 Pages) ON Semiconductor – 1 MHz, 3 A Synchronous Buck Regulator

NCP1593A, NCP1593B
ǒ Ǔ _{Vin @ Iout @ tr ) tf @ fSW}
P_HSSW +
2
(eq. 10)
t_r and t_f are the rise and fall times of the internal power
MOSFET measured at SW node. Typical rise times are 4 ns
(rising) and 2 ns (falling).
2. Low side MOSFET
The power dissipated in the top switch is:
P_LSON + I_{RMS_LSFET} ² @ R_DS(on)LS
(eq. 11)
Where:
Ǹǒ Ǔ I_{RMS_LSFET} +
I_out
2
)
DI_PP
12
2
@ (1 * D)
(eq. 12)
DI_PP is the peak−to−peak inductor current ripple.
The switching loss for the low side MOSFET can be
ignored.
The power lost due to the quiescent current (IQ) of the device
is:
P_Q + V_in @ I_Q
(eq. 13)
IQ is the switching quiescent current of the NCP1593.
P_TOTAL + P_HSON ) P_HSSW ) P_LSON ) P_Q
(eq. 14)
Calculate the temperature rise of the die using the following
equation:
T_J + T_C ) ^ǒP_TOTAL @ q_JA^Ǔ
(eq. 15)
q_JC is the junction−to−case thermal resistance equal to
68°C/W. T_A is the ambient temperature and TJ is the junction
temperature, or die temperature. Solder the
underside−exposed pad to a large copper GND plane. If the
die temperature reaches the thermal shutdown threshold the
NCP1593 shut down and does not restart again until the die
temperature cools by 30°C.
Layout Consideration
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For 1.0MHz
switching frequency, switch rise and fall times are typically
in few nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path must be
kept as short as possible. Shortening the current path will
also reduce the parasitic trace inductance of approximately
25 nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the NCP1593 switch. When
operating at higher currents and input voltages, with poor
layout, this spike can generate voltages across the NCP1593
that may exceed its absolute maximum rating. A ground
plane should always be used under the switcher circuitry to
prevent interplane coupling and overall noise.
The FB component should be kept as far away as possible
from the switch node. The ground for these components
should be separated from the switch current path. Failure to
do so will result in poor stability or subharmonic like
oscillation.
Board layout also has a significant effect on thermal
resistance. Reducing the thermal resistance from ground pin
and exposed pad onto the board will reduce die temperature
and increase the power capability of the NCP1593. This is
achieved by providing as much copper area as possible
around the exposed pad. Adding multiple thermal vias under
and around this pad to an internal ground plane will also
help. Similar treatment to the inductor pads will reduce any
additional heating effects.
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