NCP1207A Datasheet, PDF (12/16 Pages) ON Semiconductor – PWM Current-Mode Controller for Free Running Quasi-Resonant Operation

NCP1207A
• If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary
winding and the V_CC pin which will disable the DSS
operation (V_CC u 10 V).
The SOIC package offers a 178°C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decrease this number: 12 mm 12 mm to drop
R_qJA down to 100°C/W with 35 mm copper thickness (1 oz)
or 6.5 mm 6.5 mm with 70 mm copper thickness (2 oz).
As one can see, we do not recommend using the SO−8
package and the DSS if the part operates at high switching
frequencies. In that case, an auxiliary winding is the best
solution.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation,
V_CC
REGULATION
OCCURS HERE
12 V
10 V
5.3 V
LATCHOFF
PHASE
NCP1207A hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in a
burst manner with a low duty−cycle. The system recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the V_CC decoupling capacitor: as soon as the
V_CC decreases from the VCC_OFF level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCC_ON level is
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 330 mA typical (I_CC3
parameter). As a result, the V_CC level slowly discharges
toward 0. When this level crosses 5.3 V typical, the
controller enters a new startup phase by turning the current
source on: V_CC rises toward 12 V and again delivers output
pulses at the VCC_OFF crossing point. If the fault condition
has been removed before VCC_ON approaches, then the IC
continues its normal operation. Otherwise, a new fault cycle
takes place. Figure 24 shows the evolution of the signals in
presence of a fault.
DRV
INTERNAL
FAULT FLAG
DRIVER
PULSES
TIME
TIME
If the fault is relaxed during the Vcc
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when Vcc
reached VCC_ON, then the controller
cuts everything off until recovery.
STARTUP PHASE
FAULT IS
RELAXED
FAULT OCCURS HERE
TIME
Figure 24.
Soft−Start
The NCP1207A features an internal 1 ms soft−start to
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as V_CC reaches VCC_OFF , the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft−start is also activated during the
overcurrent burst (OCP) sequence. Every restart attempt is
followed by a soft−start activation. Generally speaking, the
soft−start will be activated when V_CC ramps up either from
zero (fresh power−on sequence) or 5.3 V, the latchoff
voltage occurring during OCP.
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