NB3W800L Datasheet, PDF (12/16 Pages) ON Semiconductor – Differential 1:8 HCSL Compatible Push-Pull Clock ZDB/Fanout Buffer for PCIe

NB3W800L
SIGNAL AND FEATURE OPERATION
CLK_IN, CLK_IN#
The differential input clock is expected to be sourced from
a clock synthesizer with an HCSL−compatible output, e.g.
CK420BQ, CK−NET, CK−uS, or CK509B or another
driver.
OE# and Output Enables (Control Registers)
Each output can be individually enabled or disabled by
SMBus control register bits. Additionally, each output of the
DIF[7:0] has a dedicated OE# pin. The OE# pins are
asynchronous asserted−low signals. The Output Enable bits
in the SMBus registers are active high and are set to enable
by default.
The disabled state for the NB3W800L low power NMOS
Push−Pull outputs is Low/Low.
Please note that the logic level for assertion or deassertion
is different in software than it is on hardware. Output is
enabled if OE# pin is pulled low and still maintains software
programming logic with output enabled if OE register is true.
The assertion and de−assertion of this signal is absolutely
asynchronous.
OE# Assertion (Transition from ‘1’ to ‘0’)
All differential outputs that were tristated will resume
normal operation in a glitch free manner.
OE# De−Assertion (Transition from ‘0’ to ‘1’)
Corresponding output will transition from normal
operation to tri−state in a glitch free manner.
100M_133M# − Frequency Selection
The 100M_133M# is a hardware pin, which programs the
appropriate output frequency of the DIF pairs. Note that the
CLK_IN frequency is equal to CLK_OUT frequency. An
external pull−up or pull−down resistor is attached to this pin
to select the input/output frequency.
PWRGD / PWRDN#
PWRGD is asserted high and de−asserted low. De−assertion
of PWRGD (pulling the signal low) is equivalent to
indicating a powerdown condition. PWRGD (assertion) is
used by the NB3W800L to sample initial configurations
such as frequency select condition.
After PWRGD has been asserted high for the first time,
the pin becomes a PWRDN# (Power Down) pin that can be
used to shut off all clocks cleanly and instruct the device to
invoke power savings mode. PWRDN# is a completely
asynchronous active low input. When entering power
savings mode, PWRDN# should be asserted low prior to
shutting off the input clock or power to ensure all clocks shut
down in a glitch free manner.
The assertion and de−assertion of PWRDN# is absolutely
asynchronous.
When PWRDN# is sampled low by two consecutive
rising edges of DIF#, all differential outputs are held
tri−stated on the next DIF# high to low transition.
HBW_BYPASS_LBW#
The HBW_BYPASS_LBW# is a tri level function input
pin. It is used to select between PLL high bandwidth, bypass
mode and PLL low bandwidth mode.
Device Power Up Sequence
The device power up should follow the sequence
mentioned below for proper functioning of the device:
PWRGD/PWRDN# should be asserted Low. All other
Control pins should be defined to the required state. Power
should be given to the device. PWRGD/PWRDN# should be
asserted High.
Note: if no clock is present on the CLK_IN/CLK_IN#
pins, whenever device is Powered Up,there will be no clock
on DIF/DIF# outputs
POWER FILTERING EXAMPLE
V3P3
FB1
FERRITE
R1
VDDA
2.2
C9
1 mF
C7
0.1 mF
Place at pin
VDD for PLL
R2
VDDR
2.2
C10
1 mF
C8
0.1 mF
VDD for Input Receiver
C5
0.1 mF
VDD_DIF
C6
0.1 mF
VDD_DIF
C1
10 mF
C2
0.1 mF
C4
0.1 mF
C3
0.1 mF
C5
0.1 mF
C6
0.1 mF
Figure 7. Schematic Example of the NB3W800L Power Filtering
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