CS51313 Datasheet, PDF (12/23 Pages) Cherry Semiconductor Corporation – Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators

CS51313
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − COMP Pin (1.0 V/div)
Channel 3 − V_CC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 13. Startup with COMP Pre−Charge to 2.0 V
(2.0 ms/div)
Because the start−up circuitry depends on the current
sense function, a current sense resistor should always be
used.
When driving large capacitive loads, the COMP must
charge slowly enough to avoid tripping the CS51313
overcurrent protection. The following equation can be used
to ensure unconditional startup:
ICHG
CCOMP
t
ILIM * ILOAD
COUT
where:
I_CHG = COMP Source Current (30 μA typical);
C_COMP = COMP Capacitor value (0.1 μF typical);
I_LIM = Current Limit Threshold;
I_LOAD = Load Current during startup;
C_OUT = Total Output Capacitance.
Normal Operation
During normal operation, Switch Off−Time is constant
and set by the C_OFF capacitor. Switch On−Time is adjusted
by the V² Control loop to maintain regulation. This results
in changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
and the ESR of the output capacitors
Transient Response
The CS51313 V² Control Loop’s 200 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse−by−pulse adjustment
of duty cycle is provided to quickly ramp the inductor
current to the required level. Since the inductor current
cannot be changed instantaneously, regulation is maintained
by the output capacitor(s) during the time required to slew
the inductor current.
Overall load transient response is further improved
through a feature called “Adaptive Voltage Positioning.”
This technique pre−positions the output voltage to reduce
total output voltage excursions during changes in load.
Holding tolerance to 1.0% allows the error amplifiers
reference voltage to be targeted +25 mV high without
compromising DC accuracy. A “Droop Resistor,”
implemented through a PC board trace, connects the Error
Amps feedback pin (V_FB) to the output capacitors and load
and carries the output current. With no load, there is no DC
drop across this resistor, producing an output voltage
tracking the Error amps, including the +25 mV offset. When
the full load current is delivered, a 50 mV drop is developed
across this resistor. This results in output voltage being
offset −25 mV low.
The result of Adaptive Voltage Positioning is that
additional margin is provided for a load transient before
reaching the output voltage specification limits. When load
current suddenly increases from its minimum level, the
output is pre−positioned +25 mV. Conversely, when load
current suddenly decreases from its maximum level, the
output is pre−positioned −25 mV. For best Transient
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