CAT28F001 Datasheet, PDF (12/18 Pages) Catalyst Semiconductor – 1 Megabit CMOS Boot Block Flash Memory

CAT28F001
Figure 5 Block Erase Flowchart
START
WRITE 20H,
BLOCK ADDRESS
Bus
Operation Command Comments
Write
Erase
Setup
Data = 20H
Address = Within Block to be erased
WRITE D0H
BLOCK ADDRESS
READ STATUS
REGISTER
SR.7 = 1?
NO
YES
FULL STATUS
CHECK IF DESIRED
BLOCK ERASE
COMPLETED
Write
Erase
Data - D0H
Address = Within Block to be erased
ERASE SUSPEND
LOOP
NO
SUSPEND
ERASE?
YES
Read
Standby
Status Register Data.
Toggle OE or CE to update
Status Register
Check SR.7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full Status check can be done after each block or after a sequence
of blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
FULL STATUS CHECK PROCEDURE
STATUS REGISTER DATA
READ (SEE ABOVE)
SR.3 = 0?
YES
SR.4,5 = 1?
NO
SR.5 = 0?
NO
V_PP RANGE
ERROR
YES COMMAND SEQUENCE
ERROR
NO BLOCK ERASE
ERROR
BLOCK ERASE
SUCCESSFUL
Bus
Operation Command Comments
Standby
Check SR.3
1 = V_PP Low Detect
Standby
Check SR.4
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during a erase attempt, before further
attempts are allowed by the Write State Machine.
SR.3 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Doc. No. MD-1078, Rev. K
12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice