BELASIGNA250 Datasheet, PDF (12/30 Pages) ON Semiconductor – High-Performance Programmable Audio Processing System

BELASIGNA 250
Internal Power Supplies
Power management circuitry in BELASIGNA 250 generates separate digital (VDDC) and analog (VREG, VDBL) regulated
supplies. Each supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors
should be placed as close as possible to the power pads. Further details on these critical signals are provided in Table 5.
Non−critical signals are outlined in Table 6.
Table 5. CRITICAL SIGNALS
Pin Name
Description
VBAT
Power supply
VREG, VDBL
Internal regulator for analog sections
AGND
VDDO / VDDC
GNDO / GNDC
AI0, AI1 / LOUT,
AI2, AI3
Analog ground return
Internal regulator for digital sections
(pads and core)
Digital ground return (pads and core)
Microphone inputs
AIR
Input stage reference voltage
AO0, AO1
RCVR0+, RCVR0−,
RCVR1+, RCVR1−
Analog audio output
Direct digital audio output
AOR
RCVRGND
EXT_CLK
AI_RC
Output stage reference voltage
Output stage ground return
External clock input / internal clock
output
Infrared receiver input
Routing Guideline
Place 1 mF (min) decoupling capacitor close to pin. Connect
negative terminal of capacitor to DGND plane.
Place separate 1 mF decoupling capacitors close to each pin. Con-
nect negative capacitor terminal to AGND. Keep away from digital
traces and output traces. VREG may be used to generate micro-
phone bias. VDBL shall not be used to supply external circuitry.
Connect to AGND plane.
Place 10 mF decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND.
Connect to digital ground.
Keep as short as possible. Keep away from all digital traces and
audio outputs. Avoid routing in parallel with other traces. Connect
unused inputs to AGND.
Connect to AGND. If no analog ground plane, should share trace
with microphone grounds to star point.
Keep away from microphone inputs.
Keep away from analog traces, particularly microphone inputs.
Route corresponding traces as differential pair; route parallel to each
other and approximately the same length.
Connect to star point. Share trace with power amplifier (if present).
Connect to star point. Keep away from analog inputs.
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
If used, minimize trace length to photodiode.
Not available on the CABGA option
Table 6. NON−CRITICAL SIGNALS
Pin Name
Description
CAP0, CAP1
Internal charge pump − capacitor connection
DEBUG_TX, DEBUG_RX
Debug port
TWSS_SDA, TWSS_CLK
TWSS port
GPIO[14..0]
General−purpose I/O
GPIO[15]
General−purpose I/O
Determines voltage mode during boot. For 1.8 V
operation, should be connected to DGND.
UART_RX, UART_TX
General−purpose UART
PCM_FRAME, PCM_CLK,
PCM_OUT, PCM_IN
Pulse code modulation port
I2S_INA, I2S_IND, I2S_FA,
I2S_FD, I2S_OUTA, I2S_OUTD
I²S compatible port
UCLK
Programmable clock output
LSAD[5..0]
SPI_CLK, SPI_CS,
SPI_SERI, SPI_SERO
Low−speed A/D converters
Serial peripheral interface port
Connect to EEPROM
Routing Guideline
Place 100 nF capacitor close to pins
Not critical − Connect to test points
Not critical
Not critical
Not critical
Not critical
Not critical − Keep away from analog signals.
Not critical
Not critical −
If used, keep away from analog inputs/outputs
Not critical
Not critical
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