AMIS-492X0 Datasheet, PDF (12/22 Pages) ON Semiconductor – Fieldbus MAU

AMIS-492x0
The SHUNT pin is normally connected to V_CC. It is possible to insert a resister between V_CC and SHUNT to measure the shunt current.
Its value should be small enough to keep V_DS (voltage between SHUNT pin and SGND pin) larger than 2.5V (i.e., resistor must be less
than 100Ω.).
Since the internal transistor can sink as much as 25mA, no additional circuit is necessary in most cases. Note that the drain current
must not exceed 25mA because no protection is implemented for the internal transistor. If you do not need the shunt regulator, you
should connect SHUNT and SHSETIN pins to GND and open SHSET pin. Then V_CC must be supplied from another source.
4.2.2. Series Regulator
The series regulator produces a regulated voltage at the V_O pin from V_CC. If you connect SRAO and SRTR pins together, the internal
amplifier will regulate the input voltage at SRSETIN pin to equal V_REF. An internal feedback signal is generated to produce a voltage
equal to V_REF at pin SRSET. If you connect SRSET and SRSETIN pins, the series regulator supplies 3V at pin V_O. A capacitor (C_D in
Figure 5) of 5μF or larger capacity is necessary to stabilize this regulator. The capacitor is expected to have an ESR resistor for the
circuit to be stable. If the capacitor is low, a series resistor with the cap load will help stabilize the circuit).
May
Supply
VDD
CD
VO
16
SRSET
13
Series Regulator
(Internal Configuration)
Cc2
20pF
1.54Rsr
20mA (Max)
Cfb1
40pF
A7
Rsr
VCC
VREF
SRTR _{15 14} SRAO
12 ^SRSETIN
May
Supply
VDD
CD
VO
16
R4
SRSET
N/C ₁₃
R5
Series Regulator
(External Configuration)
Cc2
20pF
1.54Rsr
20mA (Max)
Cfb1
40pF
A7
Rsr
VCC
VREF
SRTR _{15 14} SRAO
12 ^SRSETIN
Figure 5: Series Regulator
The supply current must not exceed 20mA because no current limiting is applied to the internal transistor. You can increase V_O voltage
up to 3.5V by dividing V_O with an external network to supply the appropriate voltage to pin SRSETIN. In this case, pin SRSET must be
kept open. The drain-source voltage of the internal transistor must be larger or equal to 2V. If this condition is not satisfied, you may
need an external P-channel JFET to create the desired low voltage-drop regulator. The output voltage is determined by the following
equation.
VO = VREF × (1 + R4/R5)
4.2.3. Low Voltage Detectors
Low voltage detectors are included to monitor supply voltages and generate “power fail” signals. The low voltage alarms are detected
by sensing the voltage on pins SHSETIN and SRSETIN. These pins also provide feedback for the shunt and series regulators. If the
voltage on the SHSETIN pin is lower than the threshold, VTH9 (90 percent VREF), N_PFAIL1 goes low. Typically SHSETIN monitors
the analog rail voltage VCC. If the voltage on the SRSETIN pin is lower than the threshold, VTH9, N_PFAIL2 goes low. Typically
SRSETIN monitors the digital rail voltage VDD.
Both outputs are open drain, so a resistor will be required. If you do not use one of these pins, it should be connected to GND. You
can also add capacitors to delay these signals. In this case, sink current must not exceed the maximum value.
If you do not wish to use one of the low voltage detectors its corresponding output pin should be connected to GND.
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