PCA9535E Datasheet, PDF (11/20 Pages) ON Semiconductor – 16-bit Low-Power I/O Expander for I2C Bus withInterrupt

PCA9535E, PCA9535EC
BUS TRANSACTIONS
Writing to the Port Registers
To transmit data to the PCA9535E/PCA9535EC, the bus
master must first send the device address with the least
significant bit set to logic 0 (see Figure 5 “PCA9535E and
PCA9535EC device address”). The command byte is sent
after the address and determines which registers will receive
the data following the command byte.
There are eight registers within the
PCA9535E/PCA9535EC. These registers are configured to
operate as four register pairs: Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. Data
bytes are sent alternately to each register in a register pair
(see Figures 6 and 7). For example, if one byte is sent to
Output Port 1 (register 3), then the next byte will be stored
in Output Port 0 (register 2). There is no limitation on the
number of data bytes sent in one write transmission. In this
way, each 8−bit register may be updated independently of
the other registers.
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7
data to port 0
DATA 0
0.0 A 1.7
data to port 1
DATA 1
1.0 A P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
write to port
data out
from port 0
data out
from port 1
t_v(Q)
Figure 6. Write to Output Port Registers
t_v(Q)
DATA VALID
SCL 1 2 3 4 5 6 7 8 9
slave address
SDA S A6 A5 A4 A3 A2 A1 A0 0 A 0
command byte
MSB
0 0 0 0 1 1 0A
data to register
DATA 0
LSB MSB
A
data to register
DATA 1
LSB
AP
START condition
R/W ^acknowledge
from slave
acknowledge
from slave
Figure 7. Write to Configuration Registers
acknowledge
from slave
STOP
condition
Reading the Port Registers
To read data from the PCA9535E/PCA9535EC, the bus
master must first send the PCA9535E/PCA9535EC address
with the least significant bit set to logic 0 (see Figure 5
“PCA9535E and PCA9535EC device address”). The
command byte is sent after the address and determines
which register will be accessed.
After a restart, the device address must be sent again, but
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
by the PCA9535E/PCA9535EC (see Figures 8, 9 and 10).
Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read,
additional bytes may be read but with data alternately
coming from each register in the pair. For example, if you
read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data
bytes received in one read transmission but the bus master
must not acknowledge the data for the final byte received.
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