NCP81178 Datasheet, PDF (11/17 Pages) ON Semiconductor – Secondary Synchronous Rectifier Driver

NCP81178
Shutdown Detection (SDDET)
The Shutdown Detection function allows the
primary−side controller to send a shutdown signal to the
secondary−side driver. As shown in the Typical Application
Circuit in Figure 1, the SDDET pin is used to detect an
increase in volt−seconds in the main transformer. An RC
ramp circuit is connected from SDDET to the freewheeling
rectifier drain, DFW, or to an auxiliary winding on the main
transformer. When the voltage on SDDET exceeds the
shutdown detection threshold voltage, GFR and GFW are
immediately pulled low and PBSS is discharged. When
valid PWM pulses resume and V_CC is above UVLO, the
NCP81178 will go through a restart process. This is a
non−latching shutdown. Using the Shutdown Detection
function ensures both gate drives to turn off when there is
positive current through the output inductor. Turning off
both gate drives when there is negative current through the
freewheeling FET could result in excessive voltage
transients across the freewheeling FET.
Pre−bias Startup
The NCP81178 implements a pre−bias startup function. A
RC circuit (R_PBSS and C_PBSS) connected to the PBSS pin
sets the pre−bias startup ramp voltage to define the transition
process from diode rectification mode to synchronous
rectification mode. During pre−bias startup, C_PBSS is
charged by resistor R_PBSS, connected from V_CC to PBSS.
Initially, when V_CC reaches UVLO and the NCP81178 is
activated, the PBSS voltage is first discharged and then
starts to charge up. When the PBSS voltage is lower than the
PBSS onset threshold voltage (PBSS_onset_th), both gate
drives are pulled low. Once the PBSS voltage rises above
PBSS_onset_th, the GFR output follows the PWM input
while at the same time the pre−bias process is initiated and
the gate drive pulse width of the freewheeling gate drive
gradually increases from 0 to its final steady state value until
the secondary rectifier fully enters synchronous rectification
mode.
A resistor connected from RRAMP to ground sets the
discharge ramp slope for a ramp voltage within the
NCP81178. This discharge ramp (SLOW_RAMP) together
with the PBSS ramp sets the GFW pulse width in the
pre−bias startup transition process. In the pre−bias startup
process the rising edge of the GFW pulse gradually expands
backward until it meets the falling edge of the GFR pulse.
Pulling the PBSS voltage below the PBSS_onset_th voltage
disables both gate drives. Refer to Figure 7 for the key timing
waveforms for pre−bias start.
PWM
VCC UVLO
VCC
SLOW_RAMP
PBSS
PBSS_onset_th
PBSS_PWM
GFR
GFW
Figure 7. Key Waveforms And Timings For Pre−Bias Start
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