NCP3155BDR2G Datasheet, PDF (11/25 Pages) ON Semiconductor – 3 A Synchronous Buck Regulator

NCP3155A, NCP3155B
OOV and OUV
The output voltage of the buck converter is monitored at
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figures 31 and 32. All comparator outputs are
ignored during the soft−start sequence as soft−start is
regulated by the OTA and false trips would be generated.
After the soft−start period has ended, if the feedback is
below the reference voltage of comparator 2 (V_FB < 0.6 V),
the output is considered “undervoltage” and the device will
initiate a restart. When the feedback pin voltage rises
between the reference voltages of comparator 1 and
comparator 2 (0.6 < V_FB < 1.0), then the output voltage is
considered “Power Good.” Finally, if the feedback voltage
is greater than comparator 1 (V_FB > 1.0 V), the output
voltage is considered “overvoltage,” and the device will
latch off. To clear a latch fault, input voltage must be
recycled. Graphical representation of the OOV and OUV is
shown in Figures 33 and 34.
Vref*125%
Soft Start Complete
Comparator 1
Restart
FB
Vref = 0.8 V
LOGIC
Vref*75%
Comparator 2
Figure 31. OOV and OUV Circuit Diagram
Latch off
Hysteresis = 5 mV
Hysteresis = 5 mV
OOVP & Power Good = 0
Power Good = 1
Power Good = 1
OUVP & Power Good = 0
Voov = Vref * 125%
Power Not good High
Vref = 0.8 V
Power Not Good Low
Vouv = Vref * 75%
Figure 32. OOV and OUV Window Diagram
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