NCP1341 Datasheet, PDF (11/41 Pages) ON Semiconductor – High-Voltage, Quasi-Resonant, Controller Featuring Valley Lock-Out Switching

NCP1341
DRIVER
The NCP1341 maximum supply voltage, V_CC(MAX), is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
MOSFETs. The DRV voltage clamp, V_DRV(high) is typically
12 V with a maximum limit of 14 V.
REGULATION CONTROL
Peak Current Control
The NCP1341 is a peak current−mode controller, thus the
FB voltage sets the peak current flowing in the transformer
and the MOSFET. This is achieved by sensing the MOSFET
current across a resistor and applying the resulting voltage
ramp to the non−inverting input of the PWM comparator
through the CS pin. The current limit threshold is set by
applying the FB voltage divided by K_FB (typically 3) to the
inverting input of the PWM comparator. When the current
sense voltage ramp exceeds this threshold, the output driver
is turned off, however, the peak current is affected by several
functions (see Figure 7):
The peak current level is clamped during the soft−start
phase. The setpoint is actually limited by a clamp level
ramping from 0 to 1.0 V within 4 ms.
In addition to the PWM comparator, a dedicated
comparator monitors the current sense voltage, and if it
reaches the maximum value, V_ILIM (typically 1.00 V), the
gate driver is turned off and the overload timer is enabled.
This occurs even if the limit imposed by the feedback
voltage is higher than V_ILIM1. Due to the parasitic
capacitances of the MOSFET, a large voltage spike often
appears on the CS Pin at turn−on. To prevent this spike from
falsely triggering the current sense circuit, the current sense
signal is blanked for a short period of time, t_LEB1 (typically
275 ns), by a leading edge blanking (LEB) circuit. Figure 7
shows the schematic of the current sense circuit.
The peak current is also limitied to a minimum level,
V_freeze (0.2 V, typically). This results in higher efficiency at
light loads by increasing the minimum energy delivered per
switching cycle, while reducing the overall number of
switching cycles during light load.
Figure 7. Current Sense Logic
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