NCP1338 Datasheet, PDF (11/15 Pages) ON Semiconductor – PWM Current-Mode Controller for Free Running Quasi-Resonant Operation

NCP1338
Soxyless
The “Valley point detection” is based on the observation
of the Power MOSFET Drain voltage variations. When the
transformer is fully demagnetized, the Drain voltage
evolution from the plateau level down to the V_IN asymptote
is governed by the resonating energy transfer between the
L_P transformer inductor and the global capacitance present
on the Drain. These voltage oscillations create current
oscillation in the parasitic capacitor across the switching
MOSFET (modelized by the Crss capacitance between
Gate and Drain): a negative current (flowing out of DRV
pin) takes place during the decreasing part of the Drain
oscillation, and a positive current (entering into the DRV
pin) during the increasing part.
The Drain valley corresponds to the inversion of the
current (i.e., the zero crossing): by detecting this point, we
always ensure a true valley turn−on.
Isoxy
DRV
Crss
Lprim
Vswitch
T_SWING
t
Figure 6. Soxyless Concept
The current in the Power MOSFET gate is:
Igate = Vringing/Zc (with Zc the capacitance impedance)
so
Igate = Vringing S (2 S p S Fres S Crss)
The magnitude of this gate current depends on the
MOSFET, the resonating frequency and the voltage swing
present on the Drain at the end of the plateau voltage.
The dead time T_SWING is given by the equation:
Tswing + 0.5ńFres + p * ^ǸLp * Cdrain ^{(eq. 1)}
(where L_P is the primary transformer inductance and
C_DRAIN the total capacitance present on the MOSFET
Drain. This capacitance includes the snubber capacitor if
any, the transformer windings stray capacitance plus the
parasitic MOSFET capacitances C_OSS and C_RSS).
Internal Feedback Circuitry
To simplify the implementation of a primary regulation,
it is necessary to inject a current into the FB pin (instead of
sourcing it out). But to have a precise primary regulation,
the voltage present on FB pin must be regulated. Figure 8
gives the FB pin internal implementation: the circuitry
combines the functions of a current to voltage converter
and a voltage regulator.
FB
+
-
+
3V
Vdd
Internal
Setpoint
20 kHz
Low−pass Filter
Figure 7. Internal Implementation of FB Pin
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