NCN6000 Datasheet, PDF (11/36 Pages) ON Semiconductor – Compact Smart Card Interface IC

NCN6000
SMART CARD SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Symbol
Pin
Min
Typ
Max
Unit
CRD_RST @ CRD_VCC = +5.0 V
Output RESET V_OH @ Icrd_rst = −20 mA
Output RESET V_OL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
12
−
V_OH
CRD_VCC − 0.9
CRD_VCC
V
V_OL
0
0.4
V
t_R
100
ns
t_F
100
ns
CRD_RST @ Vcc = +3.0 V
Output RESET V_OH @ Icrd_rst = −20 mA
Output RESET V_OL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
CRD_CLK @ CRD_VCC = +3.0 V or +5.0 V
V_OH
CRD_VCC − 0.9
CRD_VCC
V
V_OL
0
0.4
V
t_R
100
ns
t_F
100
ns
13
−
CRD_VCC = +5.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50% "1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output V_OH @ Icrd_clk = −20 mA
Output V_OL @ Icrd_clk = 100 mA
F_CRDCLK
F_CRDDC
t_R
t_F
V_OH
V_OL
45
3.15
0
5.0
55
18
18
CRD_VCC
+0.5
MHz
%
ns
ns
V
V
CRD_VCC = +3.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50% "1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output V_OH @ Icrd_clk = −20 mA @ Cout = 30 pF
Output V_OL @ Icrd_clk = 100 mA @ Cout = 30 pF
CRD_I/O @ CRD_VCC = +5.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output V_OH @ Icrd_i/o = −20 mA
Output V_OL @ Icrd_i/o = 500 mA, V_IL = 0 V
F_CRDCLK
F_CRDDC
t_R
t_F
V_OH
V_OL
F_IO
T_RIO
T_FIO
V_OH
V_OL
40
1.85
0
14
315
CRD_VCC − 0.9
0
5.0
60
18
18
CRD_VCC
0.7
0.8
0.8
CRD_VCC
0.4
MHz
%
ns
ns
V
V
kHz
ms
ms
V
V
CRD_I/O @ CRD_VCC = +3.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output V_OH @ Icrd_i/o = −20 mA
Output V_OL @ Icrd_i/o = 500 mA, V_IL = 0 V
F_IO
T_RIO
T_FIO
V_OH
V_OL
315
kHz
0.8
ms
0.8
ms
CRD_VCC − 0.9
CRD_VCC
V
0
0.4
V
CRD_IO Pull Up Resistor @ PWR_ON = H
R_CRDPU
14
14
20
26
kW
Card Detection Debouncing Delay:
Card Insertion
Card Extraction
11
T_CRDIN
50
T_CRDOFF
50
−
150
ms
150
ms
Card Insertion or Extraction Positive Going Input
V_IHDET
11
0.70 * Vbat
−
Vbat
V
High Voltage
Card Insertion or Extraction Negative Going Input
V_ILDET
11
0
Low Voltage
−
0.30 * Vbat
V
Card Detection Bias Pull Up Current @
Vbat = 5.0 V
I_DET
11
−
10
−
mA
Output Peak Max Current Under Card Static
Icrd_iorst 12, 14
−
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
−
15
mA
Output Peak Max Current Under Card Static
Icrd_clk
13
−
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
−
70
mA
8. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over
the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz.
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