CAT9552WI Datasheet, PDF (11/17 Pages) ON Semiconductor – 16-Channel I2C-bus LED Driver with Programmable Blink Rate

CAT9552
External Reset Operation
The CAT9552 registers and the I²C state machine are
initialized to their default state when the RESET input
is held low for a minimum of t_W. CAT9552’s registers
will be held in their default state until RESET returns
to a logic HIGH state. The external Reset timing is
shown in Figure 9.
Power-On Reset Operation
The CAT9552 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state. The device is in a
reset state for V_CC less than the internal POR
threshold level (V_POR). When V_CC exceeds the V_POR
level, the reset state is released and the CAT9552
internal state machine and registers are initialized to
their default state. Thereafter V_CC must be taken
below 0.2V to reset the device.
Slave Address
Data From Port
Data From Port
SDA
S 1 1 0 0 A2 A1 A0
A
DATA 1
A
DATA 4
NA P
READ FROM
PORT
Start Condition
R/W Acknowledge
From Slave
Acknowledge
From Master
No Acknowledge Stop
From Master Condition
DATA INTO
PORT
DATA 1
DATA 2
DATA 3
t_ph
t_ps
DATA 4
Figure 8. Read Input Port Register Timing Diagram
START
SCL
SDA
30%
RESET _50%
t_REC
LEDx
ACK OR READ CYCLE
t_RESET
50%
50%
t_W
t_RESET
50% _{LED OFF}
Figure 9. R¯¯E¯S¯E¯T¯ Timing Diagram
© 2008 SCILLC. All rights reserved
11
Characteristics subject to change without notice
Doc. No. MD-9005 Rev B