NB7VPQ16M Datasheet, PDF (10/16 Pages) ON Semiconductor – 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver

NB7VPQ16M
CASCADE APPLICATION
SDOUT/SCLKOUT
SDOUT is the Serial Data output pin; SCLKOUT is the
Serial Clock output pin. These pins are the outputs of the
5−bit SDI shift register and will produce the SDIN/SCLKIN
signals after five serial clock cycles, see Figure 12. The
purpose of SDOUT and SCLKOUT is for use in cascade
applications, described below.
D3
D2 D1
D0 EQEN SDIN
DUTA
SDOUT
D3 D2
D1
D0 EQEN
SDIN
DUTB
SDOUT
1
2
3
4
5
SCLKIN
SCLKOUT
5
6
7
8
9
SCLKIN
SCLKOUT
5 Clocks
Figure 12. Simplified Cascaded Serial Data/Clock Timing Diagram
Cascaded Applications
The NB7VPQ16M can be cascaded with multiple
NB7VPQ16Ms in series for various
Equalizer/Pre−Emphasis applications, as shown in
Figure 13.
Serial Data In, SDINA, is clocked with SCLKINA into the
cascaded chain of the Pre−Emphasis and equalizer shift
registers, (DUTA, DUTB and DUTC), 5−bits per register.
Upon the rising edge of the 5^th clock of SCLKINA, the first
valid data bit (D3) and 5^th clock will exit DUTA from
SDOUTA and SCLKOUTA and will be present at SDINB
and SCLKINB of DUTB and so on.
When SLOAD is brought LOW, the PE shift registers of
all devices are enabled and data is written into the
NB7VPQ16Ms with the contents of the PE shift registers.
When the data transfer is complete, SLOAD is brought
HIGH and all NB7VPQ16Ms are updated simultaneously.
After the PE control bits are clocked into their appropriate
registers, the Low−to−High transition of SLOAD will latch
the data bits for the Pre−Emphasis DACs.
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