NB3V60113G Datasheet, PDF (10/20 Pages) ON Semiconductor – 1.8 V Programmable OmniClock Generator

NB3V60113G
Table 9. AC ELECTRICAL CHARACTERISTICS
(V_DD = 1.8 V ± 0.1 V, GND = 0 V, T_A = −40°C to 85°C, Notes 15, 16 and 19)
Symbol
Parameter
Conditions
Min
Typ
Max
fout
Single Ended Output Frequency
0.008
200
f_MOD
SS
Spread Spectrum Modulation Rate
Percent Spread Spectrum
(deviation from nominal frequency)
fclkin ≥ 6.75 MHz
Down Spread
Center Spread
30
130
0
−4
0
±3
SSstep
Percent Spread Spectrum change
step size
Down Spread step size
Center Spread step size
0.25
0.125
SSC_RED Spectral Reduction, 3rd harmonic
@SS=−0.5%, f_out = 100 MHz, fclkin =
−10
25 MHz crystal, RES BW at 30 kHz, All
Output Types
t_PU
Stabilization time from Power−up
V_DD = 1.8 V with Frequency Modulation
3.0
t_PD
Stabilization time from Power Down Time from falling edge on PD# pin to
3.0
tri−stated outputs (Asynchronous)
Eppm
Synthesis Error
Configuration Dependent
0
SINGLE ENDED OUTPUTS (V_DD = 1.8 V ± 0.1 V; T_A = −40°C to 85°C, Notes 15, 16 and 19)
t_{JITTER−1.8 V} Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
100
input , f_out = 100 MHz, SS off
(Notes 17, 19 and 21, see Figure 12)
Cycle−Cycle Peak Jitter
Configuration Dependent. 25 MHz xtal
100
input, f_out = 100 MHz, SS off
(Notes 17, 19 and 21, see Figure 12)
t_r / t_{f 1.8 V}
Rise/Fall Time
Measured between 20% to 80% with
15 pF load, f_out = 100 MHz,
V_DD = V_DDO = 1.8 V,
Max Drive
1
Min Drive
2
t_DC
Output Clock Duty Cycle
V_DD = 1.8 V;
Duty Cycle of Ref clock is 50%
PLL Clock 45
50
55
Reference Clock 40
50
60
DIFFERENTIAL OUTPUT (CLK1, CLK0) (V_DD = 1.8 V ± 0.1 V; T_A = −40°C to 85°C, Notes 15, 19 and 20)
t_{JITTER−1.8 V} Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
100
input, f_out = 100 MHz, SS off, CLK = OFF
(Notes 18, 19, and 21, see Figure 12)
Cycle−Cycle Peak to Peak Jitter
Configuration Dependent. 25 MHz xtal
100
input, f_out = 100 MHz, SS off, CLK2 = OFF
(Notes 18, 19, and 21, see Figure 12)
t_{r 1.8 V}
Rise Time
Measured between 20% to 80%
175
700
V_DD = 1.8 V
HCSL
LVDS
t_{f 1.8 V}
Fall Time
Measured between 20% to 80%
175
700
V_DD = 1.8 V
HCSL
LVDS
Unit
MHz
kHz
%
%
%
%
dB
ms
ms
ppm
ps
ns
%
ps
ps
ps
ps
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