MC14536B_06 Datasheet, PDF (10/14 Pages) ON Semiconductor – Programmable Timer

R_X
PULSE
GEN.
CLOCK
C_X
MC14536B
+V
16
6 _{8−BYPASS}
V_DD
9A
OUT 1
4
10 _B
11 _C
12 _D
2 _RESET
OUT 2
5
1 _SET
7 _{CLOCK INH}
15 _MONO−IN
14 _{OSC INH}
3 _IN1
V_SS ^{DECODE OUT}
13
8
IN₁
RESET
DECODE OUT
*t_w
POWERUP
*t_w ≈ .00247 • R_X • C_X0.85
t_w in msec
R_X in kW
C_X in pF
NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET
input low enables the chip’s internal counters. After RESET goes low, the 2ⁿ/2 negative transition of the clock input causes
DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2ⁿ x (the clock period)
intervals where n = the number of stages selected from the truth table.
Figure 12. Time Interval Configuration Using an External Clock, Reset, and
Output Monostable to Achieve a Pulse Output
(Divide−by−4 Configured)
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