MC100EP195B_14 Datasheet, PDF (10/17 Pages) ON Semiconductor – 3.3V ECL Programmable Delay Chip

MC100EP195B
Table 10. AC CHARACTERISTICS V_CC = 0 V; V_EE = −3.0 V to −3.6 V or V_CC = 3.0 V to 3.6 V; V_EE = 0 V (Note 14)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
f_max
V_outPP
t_PLH
t_PHL
Maximum Frequency
Output Voltage Amplitude
Propagation Delay
IN to Q; D(0−10) = 0, SETMIN
IN to Q; D(0−10) = 1023, SETMAX
EN to Q; D(0−10) = 0
D0 to CASCADE
610
2000
10900
1990
375
1.2
1.2
1.2
GHz
820
610 820
610 820
mV
2400 2800 2150 2500 2950 2250 2700 3050 ps
12400 13900 11500 13000 14500 12250 13750 15250
2500 2990 2130 2600 3130 2380 2800 3380
475 575 400 500 600 425 525 625
t_RANGE
Dt
Programmable Range
t_PD (max) − t_PD (min)
Step Delay (Note 15)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
8950
ps
9950 10950 9450 10450 11450 10110 11100 12110
10
16
32
65
155
310
620
1200
2500
4900
11
18
33
72
165
325
650
1300
2600
5200
ps
15
26
46
92
195
370
720
1400
2800
5500
NLIN
Non−Linearity (Note 21)
0 to 511 Decimal Values for
D[9:0] Range
512 to 1024 Decimal Values for
D[9:0] Range
1 to 1023 Decimal Values for
D[9:0] Range
$7.0
$7.0
$11
$7.0
$7.0
$11
ps
$11
$11
$18
t_SKEW
Duty Cycle Skew (Note 16)
|t_PHL−t_PLH|
25
90
25
90
ps
25
90
t_s
Setup Time
ps
D to LEN 200 −40
200 −40
200 −40
D to IN (Note 17) 500 −550
500 −590
500 −650
EN to IN (Note 18) 300 100
300 100
300 120
t_h
Hold Time
ps
LEN to D 200
50
200 40
200 30
IN to EN (Note 19) 400 −320
400 −350
400 −400
t_R
Release Time
ps
EN to IN (Note 20) 300 −150
300 −170
300 −200
SET MAX to LEN 400 180
400 200
400 210
SET MIN to LEN 350 220
350 250
350 260
t_jitter
RMS Random Clock Jitter @ 1.2 GHz
IN to Q; D(0:10) = 0 or SETMIN
IN to Q; D(0:10) = 1023 or SETMAX
0.9 2.0
1.9 5.0
1.1 2.0
2.6 5.0
ps
1.2 2.0
3.3 5.0
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V_CC − 2.0 V.
15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than ±75 mV to that IN/IN transition.
19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output re-
sponse greater than ±75 mV to that IN/IN transition.
20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
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