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LA72702NV Datasheet, PDF (10/10 Pages) Sanyo Semicon Device – Monolithic Linear IC For US TV BTSC Decoder
LA72702NV
Reference
LOW level input voltage
Parameter
HIGH level input voltage
LOW level output current
SCL clock frequency
Set-up time for a repeated START condition
Hold time START condition. After this period, the first clock pulse is generated
LOW period of the SCL clock
Rise time of both SDA and SDL signals
HIGH period of the SCL clock
Fall time of both SDA and SDL signals
Data hold time
Data set-up time
Set-up time for STOP condition
BUS free time between a STOP and START condition
Symbol
VIL
VIH
IOL
fSCL
tSU : STA
tHD : STA
tLOW
tR
tHIGH
tF
tHD : DAT
tSU : DAT
tSU : STO
tBUF
min
-0.5
2.5
0
4.7
4.0
4.7
0
4.0
0
0
250
4.0
4.7
max
unit
1.5
V
5.5
V
3.0 mA
100 kHz
μs
μs
μs
1.0 μs
μs
1.0 μs
μs
ns
μs
μs
Definition of timing
tR
tHIGH
tF
SCL
tHD:STA tSU:STA tLOW
SDA
tHD:DATA
tSU:DAT
tSU:STO tBUF
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