CAT5259_13 Datasheet, PDF (10/15 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5259
The basic sequence of the three byte instructions is
illustrated in Figure 11. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by t_WR.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
minimum of t_WR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 10. These instructions
transfer data between the host/processor and the CAT5259;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
 XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
 XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
 Gang XFR Data Register to Wiper Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
 Gang XFR Wiper Counter Register to Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 12
and 13). The Increment/Decrement command is different
from the other commands. Once the command is issued and
the CAT5259 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCL clock pulse (t_HIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the R_H terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instructions format for more detail.
SDA
0101
S ^{ID3 ID2 ID1 ID0} A3 A2 A1 A0
T
A
R Device ID
Internal
A
C
K
I3
I2
I1
I0 R1 R0 P1 P0
A
C
K
Instruction _{Register Pot/WCR}
S
T
O
P
T
Address
Opcode _{Address Address}
Figure 10. Two-byte Instruction Sequence
SDA
0 101
S
T
ID3
ID2 ID1 ID0 A3
A2 A1
A0
A
R
Device ID
T
Internal
Address
A I3
C
K
I2 I1 I0
R1 R0
P1 P0
A
C
K
Instruction _{Data Pot/WCR}
Opcode _{Register Address}
Address
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register D[7:0]
AS
CT
KO
P
Figure 11. Three-byte Instruction Sequence
SDA
0101
S ^{ID3 ID2 ID1 ID0 A3 A2 A1 A0}
T
A Device ID
Internal
R
Address
A
C
K
I3 I2 I1 I0
Instruction
Opcode
R1 R0 P1 P0 ^A
C
Data Pot/WCR ^K
Register Address
I
N
C
1
I
N
C
2
T
Address
Figure 12. Increment/Decrement Instruction Sequence
ID
NE
CC
n1
DS
ET
CO
nP
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