CAT1025WI-30-G Datasheet, PDF (10/20 Pages) ON Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset

CAT1024, CAT1025
ACKNOWLEDGE
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
The CAT1024/25 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with
a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT1024/25 begins a READ mode it
transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it
receives this acknowledge, the CAT1024/25 will
continue to transmit data. If no acknowledge is sent
by the Master, the device terminates data transmis–
sion and waits for a STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/¯W¯ bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1024/25 acknowledges once more and the
Master generates the STOP condition. At this time, the
device begins an internal programming cycle to non-
volatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
Figure 6. Acknowledge Timing
STOP BIT
SCL FROM
1
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7: Slave Address Bits
Default Configuration 1
0
1
0
0
0
0 R/W
Doc. No. MD-3008 Rev. R
10
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Characteristics subject to change without notice