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SN74LS166 Datasheet, PDF (1/8 Pages) ON Semiconductor – LOW POWER SCHOTTKY
SN74LS166
8-Bit Shift Registers
The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 74LS standard
load. By utilizing input clamping diodes, switching transients are
minimized and system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and
has a complexity of 77 equivalent gates with gated clock inputs and an
overriding clear input. The shift/load input establishes the parallel-in
or serial-in mode. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with each clock
pulse. Synchronous loading occurs on the next clock pulse when this is
low and the parallel data inputs are enabled. Serial data flow is
inhibited during parallel loading. Clocking is done on the low-to-high
level edge of the clock pulse via a two input positive NOR gate, which
permits one input to be used as a clock enable or clock inhibit function.
Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow
the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on
the clock inhibit input should only be done when the clock input is
high. A buffered direct clear input overrides all other inputs, including
the clock, and sets all flip-flops to zero.
• Synchronous Load
• Direct Overriding Clear
• Parallel to Serial Conversion
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC
Supply Voltage
TA
Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0
25
70
°C
IOH
Output Current – High
IOL
Output Current – Low
– 0.4 mA
8.0
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS166N 16 Pin DIP 2000 Units/Box
SN74LS166D
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS166/D