SN74LS109A Datasheet, PDF (1/4 Pages) ON Semiconductor – LOW POWER SCHOTTKY

SN74LS109A
Dual JK Positive
Edge-Triggered Flip-Flop
The SN74LS109A consists of two high speed completely
independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform. The JK
design allows operation as a D flip-flop by simply connecting the J and
K pins together.
MODE SELECT – TRUTH TABLE
OPERATING MODE
INPUTS
S_D C_D
J
OUTPUTS
K
Q
Q
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
h
h
H
L
H
H
l
h
q
q
H
H
h
l
q
q
H
H
l
l
L
H
* Both outputs will be HIGH while both S_D and C_D are LOW, but the output
states are unpredictable if S_D and C_D go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
V_CC
Supply Voltage
T_A
Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0
25
70
°C
I_OH
Output Current – High
I_OL
Output Current – Low
– 0.4 mA
8.0
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS109AN 16 Pin DIP 2000 Units/Box
SN74LS109AD
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS109A/D