SDTC114EET1 Datasheet, PDF (1/13 Pages) ON Semiconductor – Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

DTC114EET1 Series,
SDTC114EET1 Series
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC−75/SOT−416 package which is designed for low power surface
mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SC−75/SOT−416 Package Can be Soldered Using Wave or
Reflow
• The Modified Gull−Winged Leads Absorb Thermal Stress During
Soldering Eliminating the Possibility of Damage to the Die
• Pb−Free Packages are Available
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
Symbol
V_CBO
V_CEO
I_C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
Rating
Total Device Dissipation,
FR−4 Board (Note 1) @ T_A = 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient (Note 1)
Symbol
P_D
R_qJA
Value
200
1.6
600
Unit
mW
mW/°C
°C/W
Total Device Dissipation,
FR−4 Board (Note 2) @ T_A = 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient (Note 2)
P_D
R_qJA
300
mW
2.4
mW/°C
400
°C/W
Junction and Storage Temperature
Range
T_J, T_stg −55 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 × 1.0 Inch Pad
© Semiconductor Components Industries, LLC, 2012
1
May, 2012 − Rev. 12
http://onsemi.com
NPN SILICON
BIAS RESISTOR TRANSISTORS
PIN 1
R1
BASE
(INPUT) _R2
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
2
1
SC−75 (SOT−416)
CASE 463
STYLE 1
MARKING DIAGRAM
xx M G
G
xx
= Specific Device Code
xx = (Refer to page 2)
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking, and shipping information in
the package dimensions section on page 2 of this data sheet.
Publication Order Number:
DTC114EET1/D